Loading asoc/codecs/bolero/rx-macro.c +9 −0 Original line number Diff line number Diff line Loading @@ -1245,6 +1245,9 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x02, 0x02); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x02, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x01, 0x01); Loading @@ -1262,6 +1265,12 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x01, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x02, 0x02); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x02, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x01, 0x00); Loading Loading
asoc/codecs/bolero/rx-macro.c +9 −0 Original line number Diff line number Diff line Loading @@ -1245,6 +1245,9 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x02, 0x02); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x02, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x01, 0x01); Loading @@ -1262,6 +1265,12 @@ static int rx_macro_mclk_enable(struct rx_macro_priv *rx_priv, regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x01, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x02, 0x02); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x02, 0x00); regmap_update_bits(regmap, BOLERO_CDC_RX_CLK_RST_CTRL_MCLK_CONTROL, 0x01, 0x00); Loading