gpio/langwell: Clear edge bit before handling

I don't have the specs for this beast, but it looks a lot like the PXA
GPIO block. Though I bet it's the same IP and the driver should have
reused the PXA code.

Acknowleding the edge detect status after handling one or more gpio
interrupts looks wrong. We might lose an edge which came in while we
handled the previous one.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Acked-by: Alek Du <alek.du@intel.com>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>