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Commit 84b919fd authored by Stephen Boyd's avatar Stephen Boyd Committed by Michael Turquette
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clk: qcom: lcc-msm8960: Fix PLL rate detection 



regmap_read() returns 0 on success, not the value of the register
that is read. Fix it so we properly detect the frequency plan.

Fixes: b82875ee "clk: qcom: Add MSM8960/APQ8064 LPASS clock
controller (LCC) driver"
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent 7dd47b8e

drivers/clk/qcom/lcc-msm8960.c

+1 −1
Original line number Diff line number Diff line
@@ -547,7 +547,7 @@ static int lcc_msm8960_probe(struct platform_device *pdev) 
		return PTR_ERR(regmap);



	/* Use the correct frequency plan depending on speed of PLL4 */

	val = regmap_read(regmap, 0x4, &val);

	regmap_read(regmap, 0x4, &val);

	if (val == 0x12) {

		slimbus_src.freq_tbl = clk_tbl_aif_osr_492;

		mi2s_osr_src.freq_tbl = clk_tbl_aif_osr_492;