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Commit 83d01b4b authored by Chinmay Sawarkar's avatar Chinmay Sawarkar
Browse files

ARM: dts: msm: Update cb address range & clocks 



Added context banks with address ranges and
removed AXIC clk. Other minor cosmetic changes.

CRs-Fixed: 2373463
Change-Id: I7a079253d53e8783adade73ac30588763dbb6994
Signed-off-by: default avatarChinmay Sawarkar <chinmays@codeaurora.org>
parent a3d9530a

arch/arm64/boot/dts/qcom/kona-vidc.dtsi

+26 −30
Original line number Diff line number Diff line
@@ -9,43 +9,39 @@ 


&soc {

	msm_vidc: qcom,vidc@aa00000 {

		compatible = "qcom,msm-vidc";

		status = "disable";

		reg = <0xaa00000 0x100000>;

		compatible = "qcom,msm-vidc", "qcom,kona-vidc";

		status = "disabled";

		reg = <0x0aa00000 0x00100000>;

		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;



		/* IOMMU Config */

		#address-cells = <1>;

		#size-cells = <1>;

		qcom,iommu-faults = "non-fatal";

		qcom,iommu-pagetables = "LLC";



		/* Supply */

		iris-ctl-supply = <&mvs0c_gdsc>;

		vcodec-supply = <&mvs0_gdsc>;



		/* Clocks */

		clock-names =  "gcc_video_axic", "gcc_video_axi0",

		clock-names =  "gcc_video_axi0",

			"ahb_clk", "xo_clk",

			"core_clk", "vcodec_clk";

		clocks = <&clock_gcc GCC_VIDEO_AXIC_CLK>,

			<&clock_gcc GCC_VIDEO_AXI0_CLK>,

		clocks = <&clock_gcc GCC_VIDEO_AXI0_CLK>,

			<&clock_videocc VIDEO_CC_AHB_CLK>,

			<&clock_videocc VIDEO_CC_XO_CLK>,

			<&clock_videocc VIDEO_CC_MVS0C_CLK>,

			<&clock_videocc VIDEO_CC_MVS0_CLK>;

		qcom,proxy-clock-names = "gcc_video_axic",

			"gcc_video_axi0",

		qcom,proxy-clock-names = "gcc_video_axi0",

					"ahb_clk", "xo_clk",

					"core_clk", "vcodec_clk";



		qcom,clock-configs = <0x0 0x0 0x0 0x0 0x1 0x1>;

		/* Mask: Bit0: Clock Scaling, Bit1: Mem Retention*/

		qcom,clock-configs = <0x0 0x0 0x0 0x1 0x1>;

		qcom,allowed-clock-rates = <240000000 338000000 366000000

						444000000 553000000>;



		/* MMUs */

		/* Firmware region */

		dma-ranges = <0x0 0x0 0x00500000>



		/* "&soc{" - Default

		 **	address-cells = 1

		 *	size-cells = 1

		 *	qcom,iommu-pagetables = "LLC"

		 *	qcom,iommu-faults = "non-fatal"

		 */

		non_secure_cb {

			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_ns";
@@ -59,10 +55,10 @@ 
			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_non_pixel";

			iommus = <&apps_smmu 0x2104 0x0400>;

			dma-ranges = <0x1000000 0x1000000 0x24800000>;

			qcom,iommu-vmid = 0xB; /*VMID_CP_NON_PIXEL*/

			dma-ranges = <0x01000000 0x01000000 0x24800000>;

			qcom,iommu-vmid = <0xB>; /*VMID_CP_NON_PIXEL*/

			buffer-types = <0x480>;

			virtual-addr-pool = <0x1000000 0x24800000>;

			virtual-addr-pool = <0x01000000 0x24800000>;

			qcom,secure-context-bank;

		};
@@ -70,10 +66,10 @@ 
			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_bitstream";

			iommus = <&apps_smmu 0x2101 0x0404>;

			dma-ranges = <0x0 0x0 0xe0000000>;

			qcom,iommu-vmid = 0x9; /*VMID_CP_BITSTREAM*/

			dma-ranges = <0x00500000 0x00500000 0xdfb00000>;

			qcom,iommu-vmid = <0x9>; /*VMID_CP_BITSTREAM*/

			buffer-types = <0x241>;

			virtual-addr-pool = <0x0 0xe0000000>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};
@@ -81,10 +77,10 @@ 
			compatible = "qcom,msm-vidc,context-bank";

			label = "venus_sec_pixel";

			iommus = <&apps_smmu 0x2103 0x0400>;

			dma-ranges = <0x0 0x0 0xe0000000>;

			qcom,iommu-vmid = 0xA; /*VMID_CP_PIXEL*/

			dma-ranges = <0x00500000 0x00500000 0xdfb00000>;

			qcom,iommu-vmid = <0xA>; /*VMID_CP_PIXEL*/

			buffer-types = <0x106>;

			virtual-addr-pool = <0x0 0xe0000000>;

			virtual-addr-pool = <0x00500000 0xdfb00000>;

			qcom,secure-context-bank;

		};

	};

arch/arm64/boot/dts/qcom/kona.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -2012,4 +2012,5 @@ 
#include "kona-camera.dtsi"

#include "kona-qupv3.dtsi"

#include "kona-thermal.dtsi"

#include "kona-vidc.dtsi"