Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 837c45bb authored by Nithin Sujir's avatar Nithin Sujir Committed by David S. Miller
Browse files

tg3: Refactor cpu pause/resume code 



The 57766 rxcpu needs to be paused/resumed when we download the firmware just
like we do for existing firmware. Refactor the pause/resume code to be
reusable.

This patch also renames the "offset" argument of tg3_halt_cpu to "cpu_base"
since that's what it really is.

Reviewed-by: default avatarBenjamin Li <benli@broadcom.com>
Signed-off-by: default avatarNithin Nayak Sujir <nsujir@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1caf13eb

drivers/net/ethernet/broadcom/tg3.c

+58 −25
Original line number Diff line number Diff line
@@ -3452,11 +3452,58 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf) 
#define TX_CPU_SCRATCH_SIZE	0x04000



/* tp->lock is held. */

static int tg3_halt_cpu(struct tg3 *tp, u32 offset)

static int tg3_pause_cpu(struct tg3 *tp, u32 cpu_base)

{

	int i;

	const int iters = 10000;



	BUG_ON(offset == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));

	for (i = 0; i < iters; i++) {

		tw32(cpu_base + CPU_STATE, 0xffffffff);

		tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);

		if (tr32(cpu_base + CPU_MODE) & CPU_MODE_HALT)

			break;

	}



	return (i == iters) ? -EBUSY : 0;

}



/* tp->lock is held. */

static int tg3_rxcpu_pause(struct tg3 *tp)

{

	int rc = tg3_pause_cpu(tp, RX_CPU_BASE);



	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);

	tw32_f(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);

	udelay(10);



	return rc;

}



/* tp->lock is held. */

static int tg3_txcpu_pause(struct tg3 *tp)

{

	return tg3_pause_cpu(tp, TX_CPU_BASE);

}



/* tp->lock is held. */

static void tg3_resume_cpu(struct tg3 *tp, u32 cpu_base)

{

	tw32(cpu_base + CPU_STATE, 0xffffffff);

	tw32_f(cpu_base + CPU_MODE,  0x00000000);

}



/* tp->lock is held. */

static void tg3_rxcpu_resume(struct tg3 *tp)

{

	tg3_resume_cpu(tp, RX_CPU_BASE);

}



/* tp->lock is held. */

static int tg3_halt_cpu(struct tg3 *tp, u32 cpu_base)

{

	int rc;



	BUG_ON(cpu_base == TX_CPU_BASE && tg3_flag(tp, 5705_PLUS));



	if (tg3_asic_rev(tp) == ASIC_REV_5906) {

		u32 val = tr32(GRC_VCPU_EXT_CTRL);
@@ -3464,17 +3511,8 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) 
		tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);

		return 0;

	}

	if (offset == RX_CPU_BASE) {

		for (i = 0; i < 10000; i++) {

			tw32(offset + CPU_STATE, 0xffffffff);

			tw32(offset + CPU_MODE,  CPU_MODE_HALT);

			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)

				break;

		}



		tw32(offset + CPU_STATE, 0xffffffff);

		tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);

		udelay(10);

	if (cpu_base == RX_CPU_BASE) {

		rc = tg3_rxcpu_pause(tp);

	} else {

		/*

		 * There is only an Rx CPU for the 5750 derivative in the
@@ -3483,17 +3521,12 @@ static int tg3_halt_cpu(struct tg3 *tp, u32 offset) 
		if (tg3_flag(tp, IS_SSB_CORE))

			return 0;



		for (i = 0; i < 10000; i++) {

			tw32(offset + CPU_STATE, 0xffffffff);

			tw32(offset + CPU_MODE,  CPU_MODE_HALT);

			if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)

				break;

		}

		rc = tg3_txcpu_pause(tp);

	}



	if (i >= 10000) {

	if (rc) {

		netdev_err(tp->dev, "%s timed out, %s CPU\n",

			   __func__, offset == RX_CPU_BASE ? "RX" : "TX");

			   __func__, cpu_base == RX_CPU_BASE ? "RX" : "TX");

		return -ENODEV;

	}
@@ -3604,8 +3637,8 @@ static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp) 
			   tr32(RX_CPU_BASE + CPU_PC), info.fw_base);

		return -ENODEV;

	}

	tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);

	tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);



	tg3_rxcpu_resume(tp);



	return 0;

}
@@ -3667,8 +3700,8 @@ static int tg3_load_tso_firmware(struct tg3 *tp) 
			   __func__, tr32(cpu_base + CPU_PC), info.fw_base);

		return -ENODEV;

	}

	tw32(cpu_base + CPU_STATE, 0xffffffff);

	tw32_f(cpu_base + CPU_MODE,  0x00000000);



	tg3_resume_cpu(tp, cpu_base);

	return 0;

}