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Commit 8376a1df authored by Ben Zhang's avatar Ben Zhang Committed by Greg Kroah-Hartman
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ASoC: rt5677: Mark reg RT5677_PWR_ANLG2 as volatile 



[ Upstream commit eabf424f7b60246c76dcb0ea6f1e83ef9abbeaa6 ]

The codec dies when RT5677_PWR_ANLG2(MX-64h) is set to 0xACE1
while it's streaming audio over SPI. The DSP firmware turns
on PLL2 (MX-64 bit 8) when SPI streaming starts.  However regmap
does not believe that register can change by itself. When
BST1 (bit 15) is turned on with regmap_update_bits(), it doesn't
read the register first before write, so PLL2 power bit is
cleared by accident.

Marking MX-64h as volatile in regmap solved the issue.

Signed-off-by: default avatarBen Zhang <benzh@chromium.org>
Signed-off-by: default avatarCurtis Malainey <cujomalainey@chromium.org>
Link: https://lore.kernel.org/r/20191106011335.223061-6-cujomalainey@chromium.org


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent b9929a59

sound/soc/codecs/rt5677.c

+1 −0
Original line number Diff line number Diff line
@@ -297,6 +297,7 @@ static bool rt5677_volatile_register(struct device *dev, unsigned int reg) 
	case RT5677_I2C_MASTER_CTRL7:

	case RT5677_I2C_MASTER_CTRL8:

	case RT5677_HAP_GENE_CTRL2:

	case RT5677_PWR_ANLG2: /* Modified by DSP firmware */

	case RT5677_PWR_DSP_ST:

	case RT5677_PRIV_DATA:

	case RT5677_ASRC_22: