Loading drivers/clk/qcom/clk-alpha-pll.c +7 −1 Original line number Diff line number Diff line Loading @@ -2310,7 +2310,13 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); if (!(regval & ALPHA_PLL_ACK_LATCH)) { if (!(regval & PLL_UPDATE_BYPASS)) { ret = wait_for_pll_update(pll); if (ret) WARN_CLK(hw->core, clk_hw_get_name(hw), 1, "PLL Update clear failed\n"); return ret; } else if (!(regval & ALPHA_PLL_ACK_LATCH)) { WARN_CLK(hw->core, clk_hw_get_name(hw), 1, "PLL latch failed. Output may be unstable!\n"); return -EINVAL; Loading Loading
drivers/clk/qcom/clk-alpha-pll.c +7 −1 Original line number Diff line number Diff line Loading @@ -2310,7 +2310,13 @@ static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate, /* Wait for 2 reference cycles before checking the ACK bit. */ udelay(1); regmap_read(pll->clkr.regmap, PLL_MODE(pll), ®val); if (!(regval & ALPHA_PLL_ACK_LATCH)) { if (!(regval & PLL_UPDATE_BYPASS)) { ret = wait_for_pll_update(pll); if (ret) WARN_CLK(hw->core, clk_hw_get_name(hw), 1, "PLL Update clear failed\n"); return ret; } else if (!(regval & ALPHA_PLL_ACK_LATCH)) { WARN_CLK(hw->core, clk_hw_get_name(hw), 1, "PLL latch failed. Output may be unstable!\n"); return -EINVAL; Loading