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Commit 8337206d authored by Damien Lespiau's avatar Damien Lespiau Committed by Ville Syrjälä
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drm/i915/skl: Expose DC5/DC6 entry counts 



The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.

v2: Rebase
v3: Take RPM ref before reading (Imre)

Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> (v1)
Signed-off-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1446220412-32574-1-git-send-email-mika.kuoppala@intel.com


Tested-by: Daniel Stone <daniels@collabora.com> # SKL
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent b7cec66d

drivers/gpu/drm/i915/i915_debugfs.c

+11 −0
Original line number Diff line number Diff line
@@ -2811,6 +2811,17 @@ static int i915_dmc_info(struct seq_file *m, void *unused) 
	seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),

		   CSR_VERSION_MINOR(csr->version));



	intel_runtime_pm_get(dev_priv);



	if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {

		seq_printf(m, "DC3 -> DC5 count: %d\n",

			   I915_READ(SKL_CSR_DC3_DC5_COUNT));

		seq_printf(m, "DC5 -> DC6 count: %d\n",

			   I915_READ(SKL_CSR_DC5_DC6_COUNT));

	}



	intel_runtime_pm_put(dev_priv);



	return 0;

}

drivers/gpu/drm/i915/i915_reg.h

+4 −0
Original line number Diff line number Diff line
@@ -5697,6 +5697,10 @@ enum skl_disp_power_wells { 
#define GAMMA_MODE_MODE_12BIT	(2 << 0)

#define GAMMA_MODE_MODE_SPLIT	(3 << 0)



/* DMC/CSR */

#define SKL_CSR_DC3_DC5_COUNT	0x80030

#define SKL_CSR_DC5_DC6_COUNT	0x8002C



/* interrupts */

#define DE_MASTER_IRQ_CONTROL   (1 << 31)

#define DE_SPRITEB_FLIP_DONE    (1 << 29)