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Commit 824da016 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-fixes-2018-08-06' of... 

Merge tag 'drm-intel-next-fixes-2018-08-06' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-next

- Fix gvt compilation broken on a silent conflict on fixes vs next merge
- Fix runtime PM for LPE audio
- Revert on ICL workaround
- Interactive RPS mode
- Fix for PSR sink status report

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180806233034.GA20655@intel.com
parents 8dd931f4 3237c0db

drivers/gpu/drm/i915/gvt/kvmgt.c

+0 −6
Original line number Diff line number Diff line
@@ -185,12 +185,6 @@ static int gvt_dma_map_page(struct intel_vgpu *vgpu, unsigned long gfn, 
	if (ret)

		return ret;



	if (!pfn_valid(pfn)) {

		gvt_vgpu_err("pfn 0x%lx is not mem backed\n", pfn);

		vfio_unpin_pages(mdev_dev(vgpu->vdev.mdev), &gfn, 1);

		return -EINVAL;

	}



	/* Setup DMA mapping. */

	*dma_addr = dma_map_page(dev, page, 0, size, PCI_DMA_BIDIRECTIONAL);

	ret = dma_mapping_error(dev, *dma_addr);

drivers/gpu/drm/i915/i915_debugfs.c

+19 −7
Original line number Diff line number Diff line
@@ -1218,7 +1218,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
			   rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));

		seq_printf(m, "RP PREV UP: %d (%dus)\n",

			   rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));

		seq_printf(m, "Up threshold: %d%%\n", rps->up_threshold);

		seq_printf(m, "Up threshold: %d%%\n",

			   rps->power.up_threshold);



		seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",

			   rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
@@ -1226,7 +1227,8 @@ static int i915_frequency_info(struct seq_file *m, void *unused) 
			   rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));

		seq_printf(m, "RP PREV DOWN: %d (%dus)\n",

			   rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));

		seq_printf(m, "Down threshold: %d%%\n", rps->down_threshold);

		seq_printf(m, "Down threshold: %d%%\n",

			   rps->power.down_threshold);



		max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :

			    rp_state_cap >> 16) & 0xff;
@@ -2218,6 +2220,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) 
	seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));

	seq_printf(m, "Boosts outstanding? %d\n",

		   atomic_read(&rps->num_waiters));

	seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));

	seq_printf(m, "Frequency requested %d\n",

		   intel_gpu_freq(dev_priv, rps->cur_freq));

	seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
@@ -2261,13 +2264,13 @@ static int i915_rps_boost_info(struct seq_file *m, void *data) 
		intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);



		seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",

			   rps_power_to_str(rps->power));

			   rps_power_to_str(rps->power.mode));

		seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",

			   rpup && rpupei ? 100 * rpup / rpupei : 0,

			   rps->up_threshold);

			   rps->power.up_threshold);

		seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",

			   rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,

			   rps->down_threshold);

			   rps->power.down_threshold);

	} else {

		seq_puts(m, "\nRPS Autotuning inactive\n");

	}
@@ -2606,13 +2609,22 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) 
		"sink internal error",

	};

	struct drm_connector *connector = m->private;

	struct drm_i915_private *dev_priv = to_i915(connector->dev);

	struct intel_dp *intel_dp =

		enc_to_intel_dp(&intel_attached_encoder(connector)->base);

	int ret;



	if (!CAN_PSR(dev_priv)) {

		seq_puts(m, "PSR Unsupported\n");

		return -ENODEV;

	}



	if (connector->status != connector_status_connected)

		return -ENODEV;



	if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val) == 1) {

	ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_STATUS, &val);



	if (ret == 1) {

		const char *str = "unknown";



		val &= DP_PSR_SINK_STATE_MASK;
@@ -2620,7 +2632,7 @@ static int i915_psr_sink_status_show(struct seq_file *m, void *data) 
			str = sink_status[val];

		seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val, str);

	} else {

		DRM_ERROR("dpcd read (at %u) failed\n", DP_PSR_STATUS);

		return ret;

	}



	return 0;

drivers/gpu/drm/i915/i915_drv.h

+12 −4
Original line number Diff line number Diff line
@@ -779,11 +779,17 @@ struct intel_rps { 
	u8 rp0_freq;		/* Non-overclocked max frequency. */

	u16 gpll_ref_freq;	/* vlv/chv GPLL reference frequency */



	int last_adj;



	struct {

		struct mutex mutex;



		enum { LOW_POWER, BETWEEN, HIGH_POWER } mode;

		unsigned int interactive;



		u8 up_threshold; /* Current %busy required to uplock */

		u8 down_threshold; /* Current %busy required to downclock */



	int last_adj;

	enum { LOW_POWER, BETWEEN, HIGH_POWER } power;

	} power;



	bool enabled;

	atomic_t num_waiters;
@@ -3422,6 +3428,8 @@ extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); 
extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val);

extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv);

extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val);

extern void intel_rps_mark_interactive(struct drm_i915_private *i915,

				       bool interactive);

extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv,

				  bool enable);

drivers/gpu/drm/i915/i915_irq.c

+2 −2
Original line number Diff line number Diff line
@@ -1265,9 +1265,9 @@ static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir) 
		c0 = max(render, media);

		c0 *= 1000 * 100 << 8; /* to usecs and scale to threshold% */



		if (c0 > time * rps->up_threshold)

		if (c0 > time * rps->power.up_threshold)

			events = GEN6_PM_RP_UP_THRESHOLD;

		else if (c0 < time * rps->down_threshold)

		else if (c0 < time * rps->power.down_threshold)

			events = GEN6_PM_RP_DOWN_THRESHOLD;

	}

drivers/gpu/drm/i915/i915_reg.h

+0 −3
Original line number Diff line number Diff line
@@ -2780,9 +2780,6 @@ enum i915_power_well_id { 
#define   GEN8_4x4_STC_OPTIMIZATION_DISABLE	(1 << 6)

#define   GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE	(1 << 1)



#define GEN10_CACHE_MODE_SS			_MMIO(0xe420)

#define   FLOAT_BLEND_OPTIMIZATION_ENABLE	(1 << 4)



#define GEN6_BLITTER_ECOSKPD	_MMIO(0x221d0)

#define   GEN6_BLITTER_LOCK_SHIFT			16

#define   GEN6_BLITTER_FBC_NOTIFY			(1 << 3)