Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 81cd5ae3 authored by Anton Blanchard's avatar Anton Blanchard Committed by Paul Mackerras
Browse files

powerpc: perf_event: Enable SDAR in continous sample mode 



In continuous sampling mode we want the SDAR to update.  While we can
select between dcache misses and ERAT (L1-TLB) misses, a decent default
is to enable both.

Signed-off-by: default avatarAnton Blanchard <anton@samba.org>
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
parent bc284e5d

arch/powerpc/include/asm/reg.h

+2 −0
Original line number Diff line number Diff line
@@ -489,6 +489,8 @@ 
#define SPRN_MMCR1	798

#define SPRN_MMCRA	0x312

#define   MMCRA_SDSYNC	0x80000000UL /* SDAR synced with SIAR */

#define   MMCRA_SDAR_DCACHE_MISS 0x40000000UL

#define   MMCRA_SDAR_ERAT_MISS   0x20000000UL

#define   MMCRA_SIHV	0x10000000UL /* state of MSR HV when SIAR set */

#define   MMCRA_SIPR	0x08000000UL /* state of MSR PR when SIAR set */

#define   MMCRA_SLOT	0x07000000UL /* SLOT bits (37-39) */

arch/powerpc/kernel/power5+-pmu.c

+0 −4
Original line number Diff line number Diff line
@@ -72,10 +72,6 @@ 
#define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)

#define MMCR1_PMCSEL_MSK	0x7f



/*

 * Bits in MMCRA

 */



/*

 * Layout of constraint bits:

 * 6666555555555544444444443333333333222222222211111111110000000000

arch/powerpc/kernel/power5-pmu.c

+1 −5
Original line number Diff line number Diff line
@@ -72,10 +72,6 @@ 
#define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)

#define MMCR1_PMCSEL_MSK	0x7f



/*

 * Bits in MMCRA

 */



/*

 * Layout of constraint bits:

 * 6666555555555544444444443333333333222222222211111111110000000000
@@ -390,7 +386,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, 
			       unsigned int hwc[], unsigned long mmcr[])

{

	unsigned long mmcr1 = 0;

	unsigned long mmcra = 0;

	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;

	unsigned int pmc, unit, byte, psel;

	unsigned int ttm, grp;

	int i, isbus, bit, grsel;

arch/powerpc/kernel/power6-pmu.c

+1 −1
Original line number Diff line number Diff line
@@ -178,7 +178,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, 
			   unsigned int hwc[], unsigned long mmcr[])

{

	unsigned long mmcr1 = 0;

	unsigned long mmcra = 0;

	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;

	int i;

	unsigned int pmc, ev, b, u, s, psel;

	unsigned int ttmset = 0;

arch/powerpc/kernel/power7-pmu.c

+1 −5
Original line number Diff line number Diff line
@@ -50,10 +50,6 @@ 
#define MMCR1_PMCSEL_SH(n)	(MMCR1_PMC1SEL_SH - (n) * 8)

#define MMCR1_PMCSEL_MSK	0xff



/*

 * Bits in MMCRA

 */



/*

 * Layout of constraint bits:

 * 6666555555555544444444443333333333222222222211111111110000000000
@@ -230,7 +226,7 @@ static int power7_compute_mmcr(u64 event[], int n_ev, 
			       unsigned int hwc[], unsigned long mmcr[])

{

	unsigned long mmcr1 = 0;

	unsigned long mmcra = 0;

	unsigned long mmcra = MMCRA_SDAR_DCACHE_MISS | MMCRA_SDAR_ERAT_MISS;

	unsigned int pmc, unit, combine, l2sel, psel;

	unsigned int pmc_inuse = 0;

	int i;