Merge 227ed6d234e0d6a89c26d60abd1e424fd7b83111 on remote branch (80b3310a) · Commits · e / devices / android_kernel_fairphone_FP4

arch/arm64/configs/vendor/kona-perf_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -719,6 +719,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y
		CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
		CONFIG_CRYPTO_DEV_QCRYPTO=y
		CONFIG_CRYPTO_DEV_QCEDEV=y
		CONFIG_CRYPTO_DEV_QCOM_ICE=y
		CONFIG_PRINTK_TIME=y
		CONFIG_DEBUG_INFO=y
		CONFIG_DEBUG_FS=y

arch/arm64/configs/vendor/kona_defconfig

+1 −0

Original line number	Diff line number	Diff line
		@@ -756,6 +756,7 @@ CONFIG_CRYPTO_ANSI_CPRNG=y
		CONFIG_CRYPTO_DEV_QCOM_MSM_QCE=y
		CONFIG_CRYPTO_DEV_QCRYPTO=y
		CONFIG_CRYPTO_DEV_QCEDEV=y
		CONFIG_CRYPTO_DEV_QCOM_ICE=y
		CONFIG_XZ_DEC=y
		CONFIG_PRINTK_TIME=y
		CONFIG_DYNAMIC_DEBUG=y

drivers/gpu/msm/kgsl_pwrctrl.c

+23 −7

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
		* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
		*/

		#include <linux/msm-bus.h>
		@@ -791,16 +792,19 @@ static ssize_t thermal_pwrlevel_store(struct device *dev,
		if (ret)
		return ret;

		mutex_lock(&device->mutex);

		if (level > pwr->num_pwrlevels - 2)
		level = pwr->num_pwrlevels - 2;

		if (kgsl_pwr_limits_set_freq(pwr->sysfs_pwr_limit,
		pwr->pwrlevels[level].gpu_freq)) {
		dev_err(device->dev,
		"Failed to set sysfs thermal limit via limits fw\n");
		mutex_lock(&device->mutex);
		pwr->thermal_pwrlevel = level;

		/* Update the current level using the new limit */
		kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
		mutex_unlock(&device->mutex);
		}

		return count;
		}
		@@ -2426,6 +2430,14 @@ int kgsl_pwrctrl_init(struct kgsl_device *device)
		if (result)
		goto error_cleanup_bus_ib;

		pwr->cooling_pwr_limit = kgsl_pwr_limits_add(KGSL_DEVICE_3D0);
		if (IS_ERR_OR_NULL(pwr->cooling_pwr_limit)) {
		dev_err(device->dev, "Failed to add cooling power limit\n");
		result = -EINVAL;
		pwr->cooling_pwr_limit = NULL;
		goto error_cleanup_bus_ib;
		}

		INIT_WORK(&pwr->thermal_cycle_ws, kgsl_thermal_cycle);
		timer_setup(&pwr->thermal_timer, kgsl_thermal_timer, 0);

		@@ -2475,6 +2487,10 @@ void kgsl_pwrctrl_close(struct kgsl_device *device)
		kfree(pwr->sysfs_pwr_limit);
		pwr->sysfs_pwr_limit = NULL;
		}

		kgsl_pwr_limits_del(pwr->cooling_pwr_limit);
		pwr->cooling_pwr_limit = NULL;

		kfree(pwr->bus_ib);

		_close_pcl(pwr);

drivers/gpu/msm/kgsl_pwrctrl.h

+3 −0

Original line number	Diff line number	Diff line
		/* SPDX-License-Identifier: GPL-2.0-only */
		/*
		* Copyright (c) 2010-2021, The Linux Foundation. All rights reserved.
		* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
		*/
		#ifndef __KGSL_PWRCTRL_H
		#define __KGSL_PWRCTRL_H
		@@ -178,6 +179,7 @@ struct gpu_cx_ipeak_client {
		* @limits_lock - spin lock to protect limits list
		* @sysfs_pwr_limit - pointer to the sysfs limits node
		* @cx_ipeak_pwr_limit - pointer to the cx_ipeak limits node
		* @cooling_pwr_limit - pointer to the cooling framework limits node
		* isense_clk_indx - index of isense clock, 0 if no isense
		* isense_clk_on_level - isense clock rate is XO rate below this level.
		* gpu_cx_ipeak_client - CX Ipeak clients used by GPU
		@@ -237,6 +239,7 @@ struct kgsl_pwrctrl {
		spinlock_t limits_lock;
		struct kgsl_pwr_limit *sysfs_pwr_limit;
		struct kgsl_pwr_limit *cx_ipeak_pwr_limit;
		struct kgsl_pwr_limit *cooling_pwr_limit;
		unsigned int gpu_bimc_int_clk_freq;
		bool gpu_bimc_interface_enabled;
		struct gpu_cx_ipeak_client gpu_ipeak_client[2];

drivers/gpu/msm/kgsl_pwrscale.c

+13 −3

Original line number	Diff line number	Diff line
		// SPDX-License-Identifier: GPL-2.0-only
		/*
		* Copyright (c) 2010-2019, The Linux Foundation. All rights reserved.
		* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
		*/

		#include <linux/devfreq_cooling.h>
		#include <linux/slab.h>
		#include <linux/msm_kgsl.h>

		#include "kgsl_device.h"
		#include "kgsl_pwrscale.h"
		@@ -900,12 +902,20 @@ static int opp_notify(struct notifier_block *nb,
		min_level = level;
		}

		pwr->thermal_pwrlevel = max_level;
		pwr->thermal_pwrlevel_floor = min_level;

		mutex_unlock(&device->mutex);

		if (kgsl_pwr_limits_set_freq(pwr->cooling_pwr_limit,
		pwr->pwrlevels[max_level].gpu_freq)) {
		dev_err(device->dev,
		"Failed to set cooling thermal limit via limits fw\n");
		mutex_lock(&device->mutex);
		pwr->thermal_pwrlevel = max_level;
		/* Update the current level using the new limit */
		kgsl_pwrctrl_pwrlevel_change(device, pwr->active_pwrlevel);
		mutex_unlock(&device->mutex);
		}

		return 0;
		}