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Commit 80ac2912 authored by Kumar Gala's avatar Kumar Gala Committed by Linus Torvalds
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[PATCH] ppc: L2 cache prefetch fixes on 745x 



We run into problems if we blindly enable L2 prefetching without
checking that the L2 cache is actually enabled.  Additionaly, if we
disable the L2 cache we need to ensure that we disable L2 prefetching.

Signed-off-by: default avatarKumar Gala <kumar.gala@freescale.com>
Signed-off-by: default avatarBenjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@osdl.org>
parent 8085ce08

arch/ppc/kernel/cpu_setup_6xx.S

+4 −1
Original line number Original line Diff line number Diff line
@@ -249,8 +249,11 @@ END_FTR_SECTION_IFSET(CPU_FTR_NO_DPM) 
	sync

	sync

	isync

	isync





	/* Enable L2 HW prefetch

	/* Enable L2 HW prefetch, if L2 is enabled

	 */

	 */

	mfspr	r3,SPRN_L2CR

	andis.	r3,r3,L2CR_L2E@h

	beqlr

	mfspr	r3,SPRN_MSSCR0

	mfspr	r3,SPRN_MSSCR0

	ori	r3,r3,3

	ori	r3,r3,3

	sync

	sync

arch/ppc/kernel/l2cr.S

+30 −1
Original line number Original line Diff line number Diff line
@@ -156,6 +156,26 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) 
	       The bit moved on the 7450.....

	       The bit moved on the 7450.....

	  ****/

	  ****/





BEGIN_FTR_SECTION

	/* Disable L2 prefetch on some 745x and try to ensure

	 * L2 prefetch engines are idle. As explained by errata

	 * text, we can't be sure they are, we just hope very hard

	 * that well be enough (sic !). At least I noticed Apple

	 * doesn't even bother doing the dcbf's here...

	 */

	mfspr	r4,SPRN_MSSCR0

	rlwinm	r4,r4,0,0,29

	sync

	mtspr	SPRN_MSSCR0,r4

	sync

	isync

	lis	r4,KERNELBASE@h

	dcbf	0,r4

	dcbf	0,r4

	dcbf	0,r4

	dcbf	0,r4

END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)



	/* TODO: use HW flush assist when available */

	/* TODO: use HW flush assist when available */





	lis	r4,0x0002

	lis	r4,0x0002
@@ -231,6 +251,15 @@ END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450) 
	mtspr	SPRN_L2CR,r3

	mtspr	SPRN_L2CR,r3

	sync

	sync

	

	

	/* Enable L2 HW prefetch on 744x/745x */

BEGIN_FTR_SECTION

	mfspr	r3,SPRN_MSSCR0

	ori	r3,r3,3

	sync

	mtspr	SPRN_MSSCR0,r3

	sync

	isync

END_FTR_SECTION_IFSET(CPU_FTR_SPEC7450)

4:

4:





	/* Restore HID0[DPM] to whatever it was before */

	/* Restore HID0[DPM] to whatever it was before */