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Commit 808ecf4a authored by Sean Wang's avatar Sean Wang Committed by Stephen Boyd
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dt-bindings: clock: mediatek: document clk bindings for MediaTek MT7622 SoC 



This patch adds the binding documentation for apmixedsys, ethsys, hifsys,
infracfg, pericfg, topckgen and audsys for MT7622.

Signed-off-by: default avatarChen Zhong <chen.zhong@mediatek.com>
Signed-off-by: default avatarSean Wang <sean.wang@mediatek.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent 5ef288d4

Documentation/devicetree/bindings/arm/mediatek/mediatek,apmixedsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -9,6 +9,7 @@ Required Properties: 
	- "mediatek,mt2701-apmixedsys"

	- "mediatek,mt2701-apmixedsys"

	- "mediatek,mt2712-apmixedsys", "syscon"

	- "mediatek,mt2712-apmixedsys", "syscon"

	- "mediatek,mt6797-apmixedsys"

	- "mediatek,mt6797-apmixedsys"

	- "mediatek,mt7622-apmixedsys"

	- "mediatek,mt8135-apmixedsys"

	- "mediatek,mt8135-apmixedsys"

	- "mediatek,mt8173-apmixedsys"

	- "mediatek,mt8173-apmixedsys"

- #clock-cells: Must be 1

- #clock-cells: Must be 1

Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.txt

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+22 −0
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MediaTek AUDSYS controller

============================



The MediaTek AUDSYS controller provides various clocks to the system.



Required Properties:



- compatible: Should be one of:

	- "mediatek,mt7622-audsys", "syscon"

- #clock-cells: Must be 1



The AUDSYS controller uses the common clk binding from

Documentation/devicetree/bindings/clock/clock-bindings.txt

The available clocks are defined in dt-bindings/clock/mt*-clk.h.



Example:



audsys: audsys@11220000 {

	compatible = "mediatek,mt7622-audsys", "syscon";

	reg = <0 0x11220000 0 0x1000>;

	#clock-cells = <1>;

};

Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -7,6 +7,7 @@ Required Properties: 




- compatible: Should be:

- compatible: Should be:

	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt2701-ethsys", "syscon"

	- "mediatek,mt7622-ethsys", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1





The ethsys controller uses the common clk binding from

The ethsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,hifsys.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -8,6 +8,7 @@ Required Properties: 




- compatible: Should be:

- compatible: Should be:

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt2701-hifsys", "syscon"

	- "mediatek,mt7622-hifsys", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1





The hifsys controller uses the common clk binding from

The hifsys controller uses the common clk binding from

Documentation/devicetree/bindings/arm/mediatek/mediatek,infracfg.txt

+1 −0
Original line number Original line Diff line number Diff line
@@ -10,6 +10,7 @@ Required Properties: 
	- "mediatek,mt2701-infracfg", "syscon"

	- "mediatek,mt2701-infracfg", "syscon"

	- "mediatek,mt2712-infracfg", "syscon"

	- "mediatek,mt2712-infracfg", "syscon"

	- "mediatek,mt6797-infracfg", "syscon"

	- "mediatek,mt6797-infracfg", "syscon"

	- "mediatek,mt7622-infracfg", "syscon"

	- "mediatek,mt8135-infracfg", "syscon"

	- "mediatek,mt8135-infracfg", "syscon"

	- "mediatek,mt8173-infracfg", "syscon"

	- "mediatek,mt8173-infracfg", "syscon"

- #clock-cells: Must be 1

- #clock-cells: Must be 1