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Commit 80815004 authored by Chen-Yu Tsai's avatar Chen-Yu Tsai Committed by Maxime Ripard
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clk: sunxi-ng: sun6i: Export video PLLs 



The 2x outputs of the 2 video PLL clocks are directly used by the
HDMI controller block.

Export them so they can be referenced in the device tree.

Fixes: c6e6c96d ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: default avatarChen-Yu Tsai <wens@csie.org>
Acked-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
parent 5da672cf

drivers/clk/sunxi-ng/ccu-sun6i-a31.h

+6 −2
Original line number Diff line number Diff line
@@ -27,7 +27,9 @@ 
#define CLK_PLL_AUDIO_4X	4

#define CLK_PLL_AUDIO_8X	5

#define CLK_PLL_VIDEO0		6

#define CLK_PLL_VIDEO0_2X	7



/* The PLL_VIDEO0_2X clock is exported */



#define CLK_PLL_VE		8

#define CLK_PLL_DDR		9
@@ -35,7 +37,9 @@ 


#define CLK_PLL_PERIPH_2X	11

#define CLK_PLL_VIDEO1		12

#define CLK_PLL_VIDEO1_2X	13



/* The PLL_VIDEO1_2X clock is exported */



#define CLK_PLL_GPU		14

#define CLK_PLL_MIPI		15

#define CLK_PLL9		16

include/dt-bindings/clock/sun6i-a31-ccu.h

+4 −0
Original line number Diff line number Diff line
@@ -43,8 +43,12 @@ 
#ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_

#define _DT_BINDINGS_CLK_SUN6I_A31_H_



#define CLK_PLL_VIDEO0_2X	7



#define CLK_PLL_PERIPH		10



#define CLK_PLL_VIDEO1_2X	13



#define CLK_CPU			18



#define CLK_AHB1_MIPIDSI	23