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Commit 8064c616 authored by Matt Weber's avatar Matt Weber Committed by Wolfram Sang
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i2c: cadance: fix ctrl/addr reg write order 



The driver was clearing the hold bit in the control register before
writing to the address register which resulted in a stop condition
being generated rather than a repeated start.

This issue was only observed when a system was running much
slower than a normal processor would execute.  The IP data sheet
mentions a ordering of writing to the address register before
clearing the hold.

Fixes: df8eb569 ("i2c: Add driver for Cadence I2C controller")
Signed-off-by: default avatarJohn Linn <john.linn@xilinx.com>
Signed-off-by: default avatarParesh Chaudhary <paresh.chaudhary@rockwellcollins.com>
Signed-off-by: default avatarMatthew Weber <matthew.weber@rockwellcollins.com>
Signed-off-by: default avatarWolfram Sang <wsa@the-dreams.de>
parent 9615a01f

drivers/i2c/busses/i2c-cadence.c

+3 −3
Original line number Diff line number Diff line
@@ -405,14 +405,14 @@ static void cdns_i2c_mrecv(struct cdns_i2c *id) 
		cdns_i2c_writereg(id->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);

	}



	/* Set the slave address in address register - triggers operation */

	cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,

						CDNS_I2C_ADDR_OFFSET);

	/* Clear the bus hold flag if bytes to receive is less than FIFO size */

	if (!id->bus_hold_flag &&

		((id->p_msg->flags & I2C_M_RECV_LEN) != I2C_M_RECV_LEN) &&

		(id->recv_count <= CDNS_I2C_FIFO_DEPTH))

			cdns_i2c_clear_bus_hold(id);

	/* Set the slave address in address register - triggers operation */

	cdns_i2c_writereg(id->p_msg->addr & CDNS_I2C_ADDR_MASK,

						CDNS_I2C_ADDR_OFFSET);

	cdns_i2c_writereg(CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);

}