Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 801382ec authored by Anirudh Ghayal's avatar Anirudh Ghayal
Browse files

power: fg-alg: Enable min/max SOC checks for weighted-CL 



Always enable min/max SOC checks to start capacity learning.
QG requires a min-SOC value to start weighted capacity
learning.

Change-Id: I9b07e5fb32f4bfc814337224bf41d44043603749
Signed-off-by: default avatarAnirudh Ghayal <aghayal@codeaurora.org>
parent eabd2e60

drivers/power/supply/qcom/fg-alg.c

+6 −6
Original line number Diff line number Diff line
@@ -486,14 +486,14 @@ static int cap_learning_begin(struct cap_learning *cl, u32 batt_soc_cp) 


	batt_soc_pct = DIV_ROUND_CLOSEST(batt_soc_cp, 100);



	if (!cl->dt.cl_wt_enable) {

		if (batt_soc_pct > cl->dt.max_start_soc ||

				batt_soc_pct < cl->dt.min_start_soc) {

	if ((cl->dt.max_start_soc != -EINVAL &&

			batt_soc_pct > cl->dt.max_start_soc) ||

			(cl->dt.min_start_soc != -EINVAL &&

			batt_soc_pct < cl->dt.min_start_soc)) {

		pr_debug("Battery SOC %d is high/low, not starting\n",

					batt_soc_pct);

		return -EINVAL;

	}

	}



	cl->init_cap_uah = div64_s64(cl->learned_cap_uah * batt_soc_cp,

					CENTI_FULL_SOC);

drivers/power/supply/qcom/qpnp-fg-gen4.c

+6 −3
Original line number Diff line number Diff line
@@ -5701,9 +5701,6 @@ static void fg_gen4_parse_cl_params_dt(struct fg_gen4_chip *chip) 
	of_property_read_u32(node, "qcom,cl-min-delta-batt-soc",

					&chip->cl->dt.min_delta_batt_soc);



	chip->cl->dt.cl_wt_enable = of_property_read_bool(node,

						"qcom,cl-wt-enable");



	chip->cl->dt.min_temp = DEFAULT_CL_MIN_TEMP_DECIDEGC;

	of_property_read_u32(node, "qcom,cl-min-temp", &chip->cl->dt.min_temp);
@@ -5727,6 +5724,12 @@ static void fg_gen4_parse_cl_params_dt(struct fg_gen4_chip *chip) 
				&chip->cl->dt.max_cap_limit);



	of_property_read_u32(node, "qcom,cl-skew", &chip->cl->dt.skew_decipct);



	if (of_property_read_bool(node, "qcom,cl-wt-enable")) {

		chip->cl->dt.cl_wt_enable = true;

		chip->cl->dt.max_start_soc = -EINVAL;

		chip->cl->dt.min_start_soc = -EINVAL;

	}

}



static int fg_gen4_parse_revid_dt(struct fg_gen4_chip *chip)

drivers/power/supply/qcom/qpnp-qg.c

+6 −2
Original line number Diff line number Diff line
@@ -3892,6 +3892,7 @@ static int qg_parse_s2_dt(struct qpnp_qg *chip) 
#define DEFAULT_CL_MIN_LIM_DECIPERC	500

#define DEFAULT_CL_MAX_LIM_DECIPERC	100

#define DEFAULT_CL_DELTA_BATT_SOC	10

#define DEFAULT_CL_WT_START_SOC		15

static int qg_parse_cl_dt(struct qpnp_qg *chip)

{

	int rc;
@@ -3959,8 +3960,11 @@ static int qg_parse_cl_dt(struct qpnp_qg *chip) 
	of_property_read_u32(node, "qcom,cl-min-delta-batt-soc",

				&chip->cl->dt.min_delta_batt_soc);



	chip->cl->dt.cl_wt_enable = of_property_read_bool(node,

						"qcom,cl-wt-enable");

	if (of_property_read_bool(node, "qcom,cl-wt-enable")) {

		chip->cl->dt.cl_wt_enable = true;

		chip->cl->dt.min_start_soc = DEFAULT_CL_WT_START_SOC;

		chip->cl->dt.max_start_soc = -EINVAL;

	}



	qg_dbg(chip, QG_DEBUG_PON, "DT: cl_min_start_soc=%d cl_max_start_soc=%d cl_min_temp=%d cl_max_temp=%d chip->cl->dt.cl_wt_enable=%d\n",

		chip->cl->dt.min_start_soc, chip->cl->dt.max_start_soc,