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Commit 7fa7ed8e authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux into next/dt 

From Jason Cooper:
mvebu dt for v3.10 round 3

 - mvebu PCIe DT support

from round 2 (no pr was sent):
 - 64bit dts skeleton
 - mvebu devicebus additions
 - mvebu thermal nodes
 - mirabox gpio leds
 - orion5x xor and ehci
 - use mvsdio on guruplug dt

* tag 'dt-3.10-3' of git://git.infradead.org/users/jcooper/linux:
  arm: mvebu: PCIe Device Tree informations for Armada XP GP
  arm: mvebu: PCIe Device Tree informations for Armada 370 DB
  arm: mvebu: PCIe Device Tree informations for Armada 370 Mirabox
  arm: mvebu: PCIe Device Tree informations for Armada XP DB
  arm: mvebu: PCIe Device Tree informations for OpenBlocks AX3-4
  arm: mvebu: add PCIe Device Tree informations for Armada XP
  arm: mvebu: add PCIe Device Tree informations for Armada 370
  ARM: dts: Add a 64 bits version of the skeleton device tree
  ARM: mvebu: Add Device Bus and CFI flash memory support to defconfig
  ARM: mvebu: Add support for NOR flash device on Openblocks AX3 board
  ARM: mvebu: Add support for NOR flash device on Armada XP-GP board
  ARM: mvebu: Add Device Bus support for Armada 370/XP SoC
  ARM: configs: Update mvebu defconfig for thermal
  ARM: mvebu: Add thermal support to Armada 370 device tree
  ARM: mvebu: Add thermal support to Armada XP device tree
  arm: mvebu: Add GPIO LEDs to Mirabox board
  arm: orion5x: enable xor for orion5x platform
  arm: orion5x: add ehci bindings to dtsi
  ARM: kirkwood: make use of DT mvsdio on guruplug board
  ARM: mvebu: Add button on Armada 370 Reference Design board
parents 3e87515a 513a7917

arch/arm/boot/dts/armada-370-db.dts

+17 −0
Original line number Diff line number Diff line
@@ -94,5 +94,22 @@ 
				spi-max-frequency = <50000000>;

			};

		};



		pcie-controller {

			status = "okay";

			/*

			 * The two PCIe units are accessible through

			 * both standard PCIe slots and mini-PCIe

			 * slots on the board.

			 */

			pcie@1,0 {

				/* Port 0, Lane 0 */

				status = "okay";

			};

			pcie@2,0 {

				/* Port 1, Lane 0 */

				status = "okay";

			};

		};

	};

};

arch/arm/boot/dts/armada-370-mirabox.dts

+53 −0
Original line number Diff line number Diff line
@@ -33,6 +33,43 @@ 
			clock-frequency = <600000000>;

			status = "okay";

		};



		pinctrl {

			pwr_led_pin: pwr-led-pin {

				marvell,pins = "mpp63";

				marvell,function = "gpo";

			};



			stat_led_pins: stat-led-pins {

				marvell,pins = "mpp64", "mpp65";

				marvell,function = "gpio";

			};

		};



		gpio_leds {

			compatible = "gpio-leds";

			pinctrl-names = "default";

			pinctrl-0 = <&pwr_led_pin &stat_led_pins>;



			green_pwr_led {

				label = "mirabox:green:pwr";

				gpios = <&gpio1 31 1>;

				linux,default-trigger = "heartbeat";

			};



			blue_stat_led {

				label = "mirabox:blue:stat";

				gpios = <&gpio2 0 1>;

				linux,default-trigger = "cpu0";

			};



			green_stat_led {

				label = "mirabox:green:stat";

				gpios = <&gpio2 1 1>;

				default-state = "off";

			};

		};



		mdio {

			phy0: ethernet-phy@0 {

				reg = <0>;
@@ -81,5 +118,21 @@ 
				reg = <0x25>;

			};

		};



		pcie-controller {

			status = "okay";



			/* Internal mini-PCIe connector */

			pcie@1,0 {

				/* Port 0, Lane 0 */

				status = "okay";

			};



			/* Connected on the PCB to a USB 3.0 XHCI controller */

			pcie@2,0 {

				/* Port 1, Lane 0 */

				status = "okay";

			};

		};

	};

};

arch/arm/boot/dts/armada-370-rd.dts

+11 −0
Original line number Diff line number Diff line
@@ -73,4 +73,15 @@ 
			status = "okay";

		};

	};



	gpio-keys {

		compatible = "gpio-keys";

		#address-cells = <1>;

		#size-cells = <0>;

		button@1 {

			label = "Software Button";

			linux,code = <116>;

			gpios = <&gpio0 6 1>;

		};

	};

};

arch/arm/boot/dts/armada-370-xp.dtsi

+45 −0
Original line number Diff line number Diff line
@@ -181,6 +181,51 @@ 
			clocks = <&coreclk 0>;

			status = "disabled";

		};



		devbus-bootcs@d0010400 {

			compatible = "marvell,mvebu-devbus";

			reg = <0xd0010400 0x8>;

			#address-cells = <1>;

			#size-cells = <1>;

			clocks = <&coreclk 0>;

			status = "disabled";

		};



		devbus-cs0@d0010408 {

			compatible = "marvell,mvebu-devbus";

			reg = <0xd0010408 0x8>;

			#address-cells = <1>;

			#size-cells = <1>;

			clocks = <&coreclk 0>;

			status = "disabled";

		};



		devbus-cs1@d0010410 {

			compatible = "marvell,mvebu-devbus";

			reg = <0xd0010410 0x8>;

			#address-cells = <1>;

			#size-cells = <1>;

			clocks = <&coreclk 0>;

			status = "disabled";

		};



		devbus-cs2@d0010418 {

			compatible = "marvell,mvebu-devbus";

			reg = <0xd0010418 0x8>;

			#address-cells = <1>;

			#size-cells = <1>;

			clocks = <&coreclk 0>;

			status = "disabled";

		};



		devbus-cs3@d0010420 {

			compatible = "marvell,mvebu-devbus";

			reg = <0xd0010420 0x8>;

			#address-cells = <1>;

			#size-cells = <1>;

			clocks = <&coreclk 0>;

			status = "disabled";

		};

	};

};

arch/arm/boot/dts/armada-370.dtsi

+58 −0
Original line number Diff line number Diff line
@@ -153,5 +153,63 @@ 
			clocks = <&coreclk 0>;

		};



		thermal@d0018300 {

			compatible = "marvell,armada370-thermal";

			reg = <0xd0018300 0x4

			       0xd0018304 0x4>;

			status = "okay";

		};



		pcie-controller {

			compatible = "marvell,armada-370-pcie";

			status = "disabled";

			device_type = "pci";



			#address-cells = <3>;

			#size-cells = <2>;



			bus-range = <0x00 0xff>;



			reg = <0xd0040000 0x2000>, <0xd0080000 0x2000>;



			reg-names = "pcie0.0", "pcie1.0";



			ranges = <0x82000000 0 0xd0040000 0xd0040000 0 0x00002000   /* Port 0.0 registers */

				  0x82000000 0 0xd0080000 0xd0080000 0 0x00002000   /* Port 1.0 registers */

				  0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */

			          0x81000000 0 0          0xe8000000 0 0x00100000>; /* downstream I/O */



			pcie@1,0 {

				device_type = "pci";

				assigned-addresses = <0x82000800 0 0xd0040000 0 0x2000>;

				reg = <0x0800 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &mpic 58>;

				marvell,pcie-port = <0>;

				marvell,pcie-lane = <0>;

				clocks = <&gateclk 5>;

				status = "disabled";

			};



			pcie@2,0 {

				device_type = "pci";

				assigned-addresses = <0x82002800 0 0xd0080000 0 0x2000>;

				reg = <0x1000 0 0 0 0>;

				#address-cells = <3>;

				#size-cells = <2>;

				#interrupt-cells = <1>;

				ranges;

				interrupt-map-mask = <0 0 0 0>;

				interrupt-map = <0 0 0 0 &mpic 62>;

				marvell,pcie-port = <1>;

				marvell,pcie-lane = <0>;

				clocks = <&gateclk 9>;

				status = "disabled";

			};

		};

	};

};