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Commit 7f9c6bce authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-alpha: Reconfigure Fabia PLL during enable 



During enable read the L value to determine if the configuration
is required again, otherwise the PLL would fail to lock or enable
due to lost/missing values.

Also update the PLL configuration, calibration and list register
functionalities.

Change-Id: Iad06657b84352915c73c509c5ef04a5f9c528598
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 004818ff

drivers/clk/qcom/clk-alpha-pll.c

+178 −4
Original line number Diff line number Diff line
@@ -94,6 +94,7 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = { 
	},

	[CLK_ALPHA_PLL_TYPE_FABIA] =  {

		[PLL_OFF_L_VAL] = 0x04,

		[PLL_OFF_CAL_L_VAL] = 0x08,

		[PLL_OFF_USER_CTL] = 0x0c,

		[PLL_OFF_USER_CTL_U] = 0x10,

		[PLL_OFF_CONFIG_CTL] = 0x14,
@@ -167,6 +168,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); 
#define ZONDA_STAY_IN_CFA	BIT(16)

#define ZONDA_PLL_FREQ_LOCK_DET	BIT(29)



/* FABIA PLL specific settings */

#define FABIA_PLL_CAL_VAL	0x3F



#define pll_alpha_width(p)					\

		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\

				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
@@ -1315,14 +1319,24 @@ const struct clk_ops clk_alpha_pll_postdiv_ro_ops = { 
};

EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_ro_ops);



void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config)

{

	u32 val, mask;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	if (config->l)

		regmap_write(regmap, PLL_L_VAL(pll), config->l);



	if (config->cal_l)

		regmap_write(regmap, PLL_CAL_L_VAL(pll), config->cal_l);

	else

		regmap_write(regmap, PLL_CAL_L_VAL(pll), FABIA_PLL_CAL_VAL);



	if (config->alpha)

		regmap_write(regmap, PLL_FRAC(pll), config->alpha);
@@ -1330,6 +1344,26 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
		regmap_write(regmap, PLL_CONFIG_CTL(pll),

						config->config_ctl_val);



	if (config->config_ctl_hi_val)

		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),

					config->config_ctl_hi_val);



	if (config->user_ctl_val)

		regmap_write(regmap, PLL_USER_CTL(pll),

					config->user_ctl_val);



	if (config->user_ctl_hi_val)

		regmap_write(regmap, PLL_USER_CTL_U(pll),

					config->user_ctl_hi_val);



	if (config->test_ctl_val)

		regmap_write(regmap, PLL_TEST_CTL(pll),

					config->test_ctl_val);



	if (config->test_ctl_hi_val)

		regmap_write(regmap, PLL_TEST_CTL_U(pll),

					config->test_ctl_hi_val);



	if (config->post_div_mask) {

		mask = config->post_div_mask;

		val = config->post_div_val;
@@ -1340,6 +1374,7 @@ void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
							PLL_UPDATE_BYPASS);



	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);

	return 0;

}

EXPORT_SYMBOL_GPL(clk_fabia_pll_configure);
@@ -1347,7 +1382,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw) 
{

	int ret;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, opmode_val;

	u32 val, opmode_val, l_val, cal_val;

	struct regmap *regmap = pll->clkr.regmap;



	ret = regmap_read(regmap, PLL_MODE(pll), &val);
@@ -1370,6 +1405,24 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw) 
	if ((opmode_val & PLL_OPMODE_RUN) && (val & PLL_OUTCTRL))

		return 0;



	ret = regmap_read(regmap, PLL_L_VAL(pll), &l_val);

	if (ret)

		return ret;



	ret = regmap_read(regmap, PLL_CAL_L_VAL(pll), &cal_val);

	if (ret)

		return ret;



	/* PLL has lost it's L or CAL value, needs reconfiguration */

	if (!l_val || !cal_val) {

		ret = clk_fabia_pll_configure(pll, regmap, pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");

	}



	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);

	if (ret)

		return ret;
@@ -1447,15 +1500,27 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 
						unsigned long prate)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, l, alpha_width = pll_alpha_width(pll);

	u32 l, cal_val, alpha_width = pll_alpha_width(pll);

	u64 a;

	unsigned long rrate;

	int ret = 0;



	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);

	ret = regmap_read(pll->clkr.regmap, PLL_CAL_L_VAL(pll), &cal_val);

	if (ret)

		return ret;



	/* PLL has lost it's CAL value, needs reconfiguration */

	if (!cal_val) {

		ret = clk_fabia_pll_configure(pll, pll->clkr.regmap,

				pll->config);

		if (ret) {

			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("%s: PLL configuration lost, reconfiguration of PLL done.\n",

				clk_hw_get_name(hw));

	}



	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);



	/*
@@ -1473,13 +1538,121 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate, 
	return __clk_alpha_pll_update_latch(pll);

}



/*

 * Fabia PLL requires power-on self calibration which happen when the PLL comes

 * out of reset. Calibration frequency is calculated by below relation:

 *

 * calibration freq = ((pll_l_valmax + pll_l_valmin) * 0.54)

 */

static int alpha_pll_fabia_prepare(struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	const struct pll_vco *vco;

	struct clk_hw *parent;

	unsigned long calibration_freq, freq_hz;

	u32 l, alpha_width = pll_alpha_width(pll), regval;

	u64 a;

	int ret;



	/* Check if calibration needs to be done i.e. PLL is in reset */

	ret = regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);

	if (ret)

		return ret;



	/* Return early if calibration is not needed. */

	if (regval & PLL_RESET_N)

		return 0;



	vco = alpha_pll_find_vco(pll, clk_hw_get_rate(hw));

	if (!vco) {

		pr_err("alpha pll: not in a valid vco range\n");

		return -EINVAL;

	}



	calibration_freq = ((pll->vco_table[0].min_freq +

				pll->vco_table[0].max_freq) * 54)/100;



	parent = clk_hw_get_parent(hw);

	if (!parent)

		return -EINVAL;



	freq_hz = alpha_pll_round_rate(calibration_freq,

			clk_hw_get_rate(parent), &l, &a, alpha_width);

	/*

	 * Due to a limited number of bits for fractional rate programming, the

	 * rounded up rate could be marginally higher than the requested rate.

	 */

	if (freq_hz > (calibration_freq + PLL_OUT_RATE_MARGIN) ||

						freq_hz < calibration_freq)

		return -EINVAL;



	/* Setup PLL for calibration frequency */

	regmap_write(pll->clkr.regmap, PLL_CAL_L_VAL(pll), FABIA_PLL_CAL_VAL);



	/* Bringup the pll at calibration frequency */

	ret = alpha_pll_fabia_enable(hw);

	if (ret) {

		pr_err("alpha pll calibration failed\n");

		return ret;

	}



	alpha_pll_fabia_disable(hw);

	return 0;

}



static void clk_fabia_pll_list_registers(struct seq_file *f, struct clk_hw *hw)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", PLL_OFF_MODE},

		{"PLL_L_VAL", PLL_OFF_L_VAL},

		{"PLL_CAL_L_VAL", PLL_OFF_CAL_L_VAL},

		{"PLL_USER_CTL", PLL_OFF_USER_CTL},

		{"PLL_USER_CTL_U", PLL_OFF_USER_CTL_U},

		{"PLL_CONFIG_CTL", PLL_OFF_CONFIG_CTL},

		{"PLL_CONFIG_CTL_U", PLL_OFF_CONFIG_CTL_U},

		{"PLL_TEST_CTL", PLL_OFF_TEST_CTL},

		{"PLL_TEST_CTL_U", PLL_OFF_TEST_CTL_U},

		{"PLL_STATUS", PLL_OFF_STATUS},

		{"PLL_OPMODE", PLL_OFF_MODE},

		{"PLL_FRAC", PLL_OFF_FRAC},

	};



	static struct clk_register_data data1[] = {

		{"APSS_PLL_VOTE", 0x0},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->offset +

					pll->regs[data[i].offset], &val);

		clock_debug_output(f, false,

				"%20s: 0x%.8x\n", data[i].name, val);

	}



	regmap_read(pll->clkr.regmap, pll->offset + pll->regs[data[0].offset],

								&val);



	if (val & PLL_FSM_ENA) {

		regmap_read(pll->clkr.regmap, pll->clkr.enable_reg +

				data1[0].offset, &val);

		clock_debug_output(f, false,

				"%20s: 0x%.8x\n", data1[0].name, val);

	}

}



const struct clk_ops clk_alpha_pll_fabia_ops = {

	.prepare = alpha_pll_fabia_prepare,

	.enable = alpha_pll_fabia_enable,

	.disable = alpha_pll_fabia_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.set_rate = alpha_pll_fabia_set_rate,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_fabia_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fabia_ops);
@@ -1490,6 +1663,7 @@ const struct clk_ops clk_alpha_pll_fixed_fabia_ops = { 
	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = alpha_pll_fabia_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.list_registers = clk_fabia_pll_list_registers,

	.bus_vote = clk_debug_bus_vote,

};

EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_fabia_ops);

drivers/clk/qcom/clk-alpha-pll.h

+1 −1
Original line number Diff line number Diff line
@@ -141,7 +141,7 @@ extern const struct clk_ops clk_alpha_pll_postdiv_zonda_ops; 


void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

			     const struct alpha_pll_config *config);

void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

int clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);

void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,

				const struct alpha_pll_config *config);