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Commit 7f93c1de authored by Charlene Liu's avatar Charlene Liu Committed by Alex Deucher
Browse files

drm/amd/display: add valid regoffset and NULL pointer check 



Signed-off-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent c1aaea99

drivers/gpu/drm/amd/display/dc/core/dc_link.c

+5 −3
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ 
#include "dc_link_dp.h"

#include "dc_link_ddc.h"

#include "link_hwss.h"

#include "opp.h"



#include "link_encoder.h"

#include "hw_sequencer.h"
@@ -2382,6 +2383,7 @@ void core_link_enable_stream( 
	core_dc->hwss.enable_audio_stream(pipe_ctx);



	/* turn off otg test pattern if enable */

	if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

		pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

				COLOR_DEPTH_UNDEFINED);

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

+5 −4
Original line number Diff line number Diff line
@@ -3,6 +3,7 @@ 
#include "dc.h"

#include "dc_link_dp.h"

#include "dm_helpers.h"

#include "opp.h"



#include "inc/core_types.h"

#include "link_hwss.h"
@@ -2511,7 +2512,7 @@ static void set_crtc_test_pattern(struct dc_link *link, 
		pipe_ctx->stream->bit_depth_params = params;

		pipe_ctx->stream_res.opp->funcs->

			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);



		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

				controller_test_pattern, color_depth);

	}
@@ -2524,7 +2525,7 @@ static void set_crtc_test_pattern(struct dc_link *link, 
		pipe_ctx->stream->bit_depth_params = params;

		pipe_ctx->stream_res.opp->funcs->

			opp_program_bit_depth_reduction(pipe_ctx->stream_res.opp, &params);



		if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)

			pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,

				CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,

				color_depth);

drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c

+4 −3
Original line number Diff line number Diff line
@@ -1475,7 +1475,7 @@ static void power_down_controllers(struct dc *dc) 
{

	int i;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

		dc->res_pool->timing_generators[i]->funcs->disable_crtc(

				dc->res_pool->timing_generators[i]);

	}
@@ -1515,12 +1515,13 @@ static void disable_vga_and_power_gate_all_controllers( 
	struct timing_generator *tg;

	struct dc_context *ctx = dc->ctx;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

	for (i = 0; i < dc->res_pool->timing_generator_count; i++) {

		tg = dc->res_pool->timing_generators[i];



		if (tg->funcs->disable_vga)

			tg->funcs->disable_vga(tg);



	}

	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		/* Enable CLOCK gating for each pipe BEFORE controller

		 * powergating. */

		enable_display_pipe_clock_gating(ctx,

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c

+5 −0
Original line number Diff line number Diff line
@@ -483,6 +483,11 @@ void hubbub1_update_dchub( 
	struct hubbub *hubbub,

	struct dchub_init_data *dh_data)

{

	if (REG(DCHUBBUB_SDPIF_FB_TOP) == 0) {

		ASSERT(false);

		/*should not come here*/

		return;

	}

	/* TODO: port code from dal2 */

	switch (dh_data->fb_mode) {

	case FRAME_BUFFER_MODE_ZFB_ONLY:

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+19 −7
Original line number Diff line number Diff line
@@ -415,6 +415,8 @@ static void dpp_pg_control( 


	if (hws->ctx->dc->debug.disable_dpp_power_gate)

		return;

	if (REG(DOMAIN1_PG_CONFIG) == 0)

		return;



	switch (dpp_inst) {

	case 0: /* DPP0 */
@@ -465,6 +467,8 @@ static void hubp_pg_control( 


	if (hws->ctx->dc->debug.disable_hubp_power_gate)

		return;

	if (REG(DOMAIN0_PG_CONFIG) == 0)

		return;



	switch (hubp_inst) {

	case 0: /* DCHUBP0 */
@@ -865,6 +869,7 @@ void hwss1_plane_atomic_disconnect(struct dc *dc, struct pipe_ctx *pipe_ctx) 
		return;



	mpc->funcs->remove_mpcc(mpc, mpc_tree_params, mpcc_to_remove);

	if (opp != NULL)

		opp->mpcc_disconnect_pending[pipe_ctx->plane_res.mpcc_inst] = true;



	dc->optimized_required = true;
@@ -1343,6 +1348,7 @@ static void dcn10_enable_per_frame_crtc_position_reset( 


	DC_SYNC_INFO("Setting up\n");

	for (i = 0; i < group_size; i++)

		if (grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset)

			grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset(

					grouped_pipes[i]->stream_res.tg,

					grouped_pipes[i]->stream->triggered_crtc_reset.event_source->status.primary_otg_inst,
@@ -2496,9 +2502,15 @@ static void dcn10_update_pending_status(struct pipe_ctx *pipe_ctx) 


static void dcn10_update_dchub(struct dce_hwseq *hws, struct dchub_init_data *dh_data)

{

	if (hws->ctx->dc->res_pool->hubbub != NULL)

	if (hws->ctx->dc->res_pool->hubbub != NULL) {

		struct hubp *hubp = hws->ctx->dc->res_pool->hubps[0];



		if (hubp->funcs->hubp_update_dchub)

			hubp->funcs->hubp_update_dchub(hubp, dh_data);

		else

			hubbub1_update_dchub(hws->ctx->dc->res_pool->hubbub, dh_data);

	}

}



static void dcn10_set_cursor_position(struct pipe_ctx *pipe_ctx)

{