Merge "mhi: controller: qcom: Enable MHI register write offload support" (7f8b56c8) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/bus/mhi/controllers/mhi_arch_qcom.c

+31 −0

Original line number	Diff line number	Diff line
		@@ -54,6 +54,37 @@ enum MHI_DEBUG_LEVEL mhi_ipc_log_lvl = MHI_MSG_LVL_ERROR;

		#endif

		void mhi_reg_write_work(struct work_struct *w)
		{
		struct mhi_controller *mhi_cntrl = container_of(w,
		struct mhi_controller,
		reg_write_work);
		struct mhi_dev *mhi_dev = mhi_controller_get_devdata(mhi_cntrl);
		struct pci_dev *pci_dev = mhi_dev->pci_dev;
		struct reg_write_info *info =
		&mhi_cntrl->reg_write_q[mhi_cntrl->read_idx];

		if (!info->valid)
		return;

		if (mhi_is_active(mhi_cntrl->mhi_dev) && msm_pcie_prevent_l1(pci_dev))
		return;

		while (info->valid) {
		if (!mhi_is_active(mhi_cntrl->mhi_dev))
		return;

		writel_relaxed(info->val, info->reg_addr);
		info->valid = false;
		mhi_cntrl->read_idx =
		(mhi_cntrl->read_idx + 1) &
		(REG_WRITE_QUEUE_LEN - 1);
		info = &mhi_cntrl->reg_write_q[mhi_cntrl->read_idx];
		}

		msm_pcie_allow_l1(pci_dev);
		}

		static int mhi_arch_pm_notifier(struct notifier_block *nb,
		unsigned long event, void *unused)
		{

drivers/bus/mhi/controllers/mhi_qcom.c

+17 −0

Original line number	Diff line number	Diff line
		@@ -840,11 +840,28 @@ static struct mhi_controller mhi_register_controller(struct pci_dev pci_dev)
		mhi_cntrl->fw_image = firmware_info->fw_image;
		mhi_cntrl->edl_image = firmware_info->edl_image;

		mhi_cntrl->offload_wq = alloc_ordered_workqueue("offload_wq",
		WQ_MEM_RECLAIM \| WQ_HIGHPRI);
		if (!mhi_cntrl->offload_wq)
		goto error_register;

		INIT_WORK(&mhi_cntrl->reg_write_work, mhi_reg_write_work);

		mhi_cntrl->reg_write_q = kcalloc(REG_WRITE_QUEUE_LEN,
		sizeof(*mhi_cntrl->reg_write_q),
		GFP_KERNEL);
		if (!mhi_cntrl->reg_write_q)
		goto error_free_wq;

		atomic_set(&mhi_cntrl->write_idx, -1);

		if (sysfs_create_group(&mhi_cntrl->mhi_dev->dev.kobj, &mhi_qcom_group))
		MHI_ERR("Error while creating the sysfs group\n");

		return mhi_cntrl;

		error_free_wq:
		destroy_workqueue(mhi_cntrl->offload_wq);
		error_register:
		mhi_free_controller(mhi_cntrl);

drivers/bus/mhi/controllers/mhi_qcom.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -67,6 +67,7 @@ struct mhi_dev {
		void mhi_deinit_pci_dev(struct mhi_controller *mhi_cntrl);
		int mhi_pci_probe(struct pci_dev *pci_dev,
		const struct pci_device_id *device_id);
		void mhi_reg_write_work(struct work_struct *w);

		#ifdef CONFIG_ARCH_QCOM

drivers/bus/mhi/core/mhi_boot.c

+15 −12

Original line number	Diff line number	Diff line
		@@ -156,13 +156,14 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl,

		MHI_LOG("BHIe programming for RDDM\n");

		mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,
		upper_32_bits(mhi_buf->dma_addr));

		mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,
		lower_32_bits(mhi_buf->dma_addr));

		mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len);
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS,
		mhi_buf->len);
		sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK;

		if (unlikely(!sequence_id))
		@@ -232,7 +233,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl)
		/* Hardware reset; force device to enter rddm */
		MHI_LOG(
		"Did not enter RDDM, do a host req. reset\n");
		mhi_write_reg(mhi_cntrl, mhi_cntrl->regs,
		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs,
		MHI_SOC_RESET_REQ_OFFSET,
		MHI_SOC_RESET_REQ);
		udelay(delayus);
		@@ -308,13 +309,14 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl,

		MHI_LOG("Starting BHIe Programming\n");

		mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,
		upper_32_bits(mhi_buf->dma_addr));

		mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,
		lower_32_bits(mhi_buf->dma_addr));

		mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len);
		mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS,
		mhi_buf->len);

		mhi_cntrl->sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK;
		mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,
		@@ -372,14 +374,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl,
		goto invalid_pm_state;
		}

		mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0);
		mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHI_STATUS, 0);
		mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,
		upper_32_bits(dma_addr));
		mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,
		mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,
		lower_32_bits(dma_addr));
		mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);
		mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);
		mhi_cntrl->session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK;
		mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id);
		mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGTXDB,
		mhi_cntrl->session_id);
		read_unlock_bh(pm_lock);

		MHI_LOG("Waiting for image transfer completion\n");

drivers/bus/mhi/core/mhi_init.c

+5 −3

Original line number	Diff line number	Diff line
		@@ -731,7 +731,7 @@ static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl)
		MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset);

		/* advertise host support */
		mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset,
		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset,
		MHI_BW_SCALE_SETUP(er_index));

		return 0;
		@@ -829,8 +829,8 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl)

		/* setup wake db */
		mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);
		mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
		mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);
		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);
		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);
		mhi_cntrl->wake_set = false;

		/* setup bw scale db */
		@@ -1437,6 +1437,8 @@ int of_register_mhi_controller(struct mhi_controller *mhi_cntrl)
		mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;
		}

		mhi_cntrl->write_reg = mhi_write_reg;

		/* read the device info if possible */
		if (mhi_cntrl->regs) {
		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,