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Commit 7f367513 authored by Sunil Paidimarri's avatar Sunil Paidimarri
Browse files

data-kernel: Add io macro settings for emac core version 2.1.1 



Change-Id: I7d661f7bb23e812783d61c63061e19f8e743efff
Acked-by: default avatarNisha Menon <nmenon@qti.qualcomm.com>
Signed-off-by: default avatarSunil Paidimarri <hisunil@codeaurora.org>
parent 892e0795

drivers/emac-dwc-eqos/DWC_ETH_QOS_mdio.c

+12 −7
Original line number Diff line number Diff line
@@ -543,7 +543,8 @@ static void set_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata, 
			EMACDBG("Read 0x%x from offset 0x8\n",phydata);

			phydata = 0;



		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2) {

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2

			|| pdata->emac_hw_version_type == EMAC_HW_v2_1_1) {

			u16 tx_clk = 0xE;

			/* Provide TX_CLK  delay of -0.06nsec */

			DWC_ETH_QOS_mdio_mmd_register_read_direct(pdata, pdata->phyaddr,
@@ -562,7 +563,8 @@ static void set_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata, 
		DWC_ETH_QOS_mdio_mmd_register_read_direct(pdata, pdata->phyaddr,

					DWC_ETH_QOS_MICREL_PHY_DEBUG_MMD_DEV_ADDR,0x5,&phydata);

		phydata &= ~(0xFF);

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

			pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

			phydata |= ((0x2 << 12) | (0x2 << 8) | (0x2 << 4) | 0x2);

		else

			/* Default settings for EMAC_HW_v2_1_0 */
@@ -579,7 +581,8 @@ static void set_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata, 
			DWC_ETH_QOS_mdio_mmd_register_read_direct(pdata, pdata->phyaddr,

					DWC_ETH_QOS_MICREL_PHY_DEBUG_MMD_DEV_ADDR,0x4,&phydata);

		phydata &= ~(0xF << 4);

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

			pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

			phydata |= (0x2 << 4);

		else

			/* Default settings for EMAC_HW_v2_1_0 */
@@ -654,9 +657,10 @@ static void configure_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata) 
			set_phy_rx_tx_delay(pdata, ENABLE_RX_DELAY, ENABLE_TX_DELAY);

		} else {

			/* Settings for RGMII ID mode.

			Not applicable for EMAC core version 2.1.0 and 2.1.2 */

			Not applicable for EMAC core version 2.1.0, 2.1.2 and 2.1.1 */

			if (pdata->emac_hw_version_type != EMAC_HW_v2_1_0 &&

				pdata->emac_hw_version_type != EMAC_HW_v2_1_2)

				pdata->emac_hw_version_type != EMAC_HW_v2_1_2 &&

				pdata->emac_hw_version_type != EMAC_HW_v2_1_1)

				set_phy_rx_tx_delay(pdata, DISABLE_RX_DELAY, DISABLE_TX_DELAY);

		}

		break;
@@ -675,9 +679,10 @@ static void configure_phy_rx_tx_delay(struct DWC_ETH_QOS_prv_data *pdata) 
				set_phy_rx_tx_delay(pdata, DISABLE_RX_DELAY, ENABLE_TX_DELAY);

			} else {

				/* Settings for RGMII ID mode */

				/* Not applicable for EMAC core version 2.1.0 and 2.1.2 */

				/* Not applicable for EMAC core version 2.1.0, 2.1.2 and 2.1.1 */

				if (pdata->emac_hw_version_type != EMAC_HW_v2_1_0 &&

					pdata->emac_hw_version_type != EMAC_HW_v2_1_2)

					pdata->emac_hw_version_type != EMAC_HW_v2_1_2 &&

					pdata->emac_hw_version_type != EMAC_HW_v2_1_1)

					set_phy_rx_tx_delay(pdata, DISABLE_RX_DELAY, DISABLE_TX_DELAY);

			}

		}

drivers/emac-dwc-eqos/DWC_ETH_QOS_platform.c

+6 −4
Original line number Diff line number Diff line
@@ -1037,8 +1037,9 @@ int DWC_ETH_QOS_enable_ptp_clk(struct device *dev) 
	int ret;

	const char* ptp_clock_name;



	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0 ||

		dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0

	    || dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2

	    || dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_1)

		ptp_clock_name = "emac_ptp_clk";

	else

		ptp_clock_name = "eth_ptp_clk";
@@ -1186,8 +1187,9 @@ static int DWC_ETH_QOS_get_clks(struct device *dev) 
	dwc_eth_qos_res_data.rgmii_clk = NULL;

	dwc_eth_qos_res_data.ptp_clk = NULL;



	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0 ||

		(dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2)) {

	if (dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_0

	    || dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_2

	    || dwc_eth_qos_res_data.emac_hw_version_type == EMAC_HW_v2_1_1) {

		/* EMAC core version 2.1.0 clocks */

		axi_clock_name = "emac_axi_clk";

		ahb_clock_name = "emac_slv_ahb_clk";

drivers/emac-dwc-eqos/DWC_ETH_QOS_rgmii_io_macro.c

+16 −7
Original line number Diff line number Diff line
@@ -364,7 +364,8 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
	uint rgmii_data_divide_clk;

	ULONG data;



	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_0 || (pdata->emac_hw_version_type == EMAC_HW_v2_3_1)) {

	if (pdata->emac_hw_version_type == EMAC_HW_v2_3_0 || (pdata->emac_hw_version_type == EMAC_HW_v2_3_1)

		|| (pdata->emac_hw_version_type == EMAC_HW_v2_1_1)) {

		if(pdata->io_macro_phy_intf == RGMII_MODE)

			loopback_mode_en = 0x1;

		rgmii_data_divide_clk = 0x0;
@@ -403,7 +404,8 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1))

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1) ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

			} else {

				/* Enable DDR mode*/
@@ -429,6 +431,8 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
					SDCC_HC_PRG_RCLK_DLY_UDFWR(52);

				else if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1)

					SDCC_HC_PRG_RCLK_DLY_UDFWR(104);

				else if (pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					SDCC_HC_PRG_RCLK_DLY_UDFWR(130);

				else { /* Program PRG_RCLK_DLY to 57 for a required delay of 1.8 ns */

					SDCC_HC_PRG_RCLK_DLY_UDFWR(57);

				}
@@ -459,9 +463,11 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1))

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1) ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

			} else{

				RGMII_DDR_MODE_UDFWR(0x1);
@@ -506,9 +512,11 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
				RGMII_LOOPBACK_EN_UDFWR(loopback_mode_en);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_0 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1))

					(pdata->emac_hw_version_type == EMAC_HW_v2_3_1) ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					RGMII_CONFIG_2_RX_PROG_SWAP_UDFWR(0x1);

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

				if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

					pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

					RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

			} else{

				RGMII_DDR_MODE_UDFWR(0x1);
@@ -570,7 +578,8 @@ int DWC_ETH_QOS_rgmii_io_macro_init(struct DWC_ETH_QOS_prv_data *pdata) 
		RGMII_CONFIG_2_DATA_DIVIDE_CLK_SEL_UDFWR(0x1);

		RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x0);

		RGMII_CONFIG_2_RERVED_CONFIG_16_EN_UDFWR(0x1);

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2)

		if (pdata->emac_hw_version_type == EMAC_HW_v2_1_2 ||

			pdata->emac_hw_version_type == EMAC_HW_v2_1_1)

			RGMII_CONFIG_2_TX_CLK_PHASE_SHIFT_EN_UDFWR(0x1);

		if (pdata->emac_hw_version_type == EMAC_HW_v2_3_1)

			RGMII_LOOPBACK_EN_UDFWR(0x1);