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Commit 7f2d479c authored by Benjamin Gaignard's avatar Benjamin Gaignard
Browse files

drm: sti: fix delay in VTG programming 



The HDMI path introduce a delay of 6 pixels.
This delay should be take into account while programming
VTG for the HDMI. Without this delay, the HDMI active
window area is shift of 6 pixel on the right.

Set also timing for DVO output.

Signed-off-by: default avatarBenjamin Gaignard <benjamin.gaignard@linaro.org>
parent ca279601

drivers/gpu/drm/sti/sti_vtg.c

+28 −3
Original line number Original line Diff line number Diff line
@@ -51,10 +51,19 @@ 
#define VTG_TOP_V_HD_3      0x010C

#define VTG_TOP_V_HD_3      0x010C

#define VTG_BOT_V_HD_3      0x0110

#define VTG_BOT_V_HD_3      0x0110





#define VTG_H_HD_4          0x0120

#define VTG_TOP_V_VD_4      0x0124

#define VTG_BOT_V_VD_4      0x0128

#define VTG_TOP_V_HD_4      0x012c

#define VTG_BOT_V_HD_4      0x0130



#define VTG_IRQ_BOTTOM      BIT(0)

#define VTG_IRQ_BOTTOM      BIT(0)

#define VTG_IRQ_TOP         BIT(1)

#define VTG_IRQ_TOP         BIT(1)

#define VTG_IRQ_MASK        (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)

#define VTG_IRQ_MASK        (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)





/* Delay introduced by the HDMI in nb of pixel */

#define HDMI_DELAY          (6)



/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */

/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */

#define AWG_DELAY_HD        (-9)

#define AWG_DELAY_HD        (-9)

#define AWG_DELAY_ED        (-8)

#define AWG_DELAY_ED        (-8)
@@ -133,10 +142,10 @@ static void vtg_set_mode(struct sti_vtg *vtg, 
	writel(tmp, vtg->regs + VTG_VID_TFS);

	writel(tmp, vtg->regs + VTG_VID_TFS);

	writel(tmp, vtg->regs + VTG_VID_BFS);

	writel(tmp, vtg->regs + VTG_VID_BFS);





	/* prepare VTG set 1 and 2 for HDMI and VTG set 3 for HD DAC */

	/* prepare VTG set 1 for HDMI */

	tmp = (mode->hsync_end - mode->hsync_start) << 16;

	tmp = (mode->hsync_end - mode->hsync_start + HDMI_DELAY) << 16;

	tmp |= HDMI_DELAY;

	writel(tmp, vtg->regs + VTG_H_HD_1);

	writel(tmp, vtg->regs + VTG_H_HD_1);

	writel(tmp, vtg->regs + VTG_H_HD_2);





	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;

	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;

	tmp |= 1;

	tmp |= 1;
@@ -146,6 +155,11 @@ static void vtg_set_mode(struct sti_vtg *vtg, 
	writel(0, vtg->regs + VTG_BOT_V_HD_1);

	writel(0, vtg->regs + VTG_BOT_V_HD_1);





	/* prepare VTG set 2 for for HD DCS */

	/* prepare VTG set 2 for for HD DCS */

	tmp = (mode->hsync_end - mode->hsync_start) << 16;

	writel(tmp, vtg->regs + VTG_H_HD_2);



	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;

	tmp |= 1;

	writel(tmp, vtg->regs + VTG_TOP_V_VD_2);

	writel(tmp, vtg->regs + VTG_TOP_V_VD_2);

	writel(tmp, vtg->regs + VTG_BOT_V_VD_2);

	writel(tmp, vtg->regs + VTG_BOT_V_VD_2);

	writel(0, vtg->regs + VTG_TOP_V_HD_2);

	writel(0, vtg->regs + VTG_TOP_V_HD_2);
@@ -166,6 +180,17 @@ static void vtg_set_mode(struct sti_vtg *vtg, 
	writel(tmp, vtg->regs + VTG_TOP_V_HD_3);

	writel(tmp, vtg->regs + VTG_TOP_V_HD_3);

	writel(tmp, vtg->regs + VTG_BOT_V_HD_3);

	writel(tmp, vtg->regs + VTG_BOT_V_HD_3);





	/* Prepare VTG set 4 for DVO */

	tmp = (mode->hsync_end - mode->hsync_start) << 16;

	writel(tmp, vtg->regs + VTG_H_HD_4);



	tmp = (mode->vsync_end - mode->vsync_start + 1) << 16;

	tmp |= 1;

	writel(tmp, vtg->regs + VTG_TOP_V_VD_4);

	writel(tmp, vtg->regs + VTG_BOT_V_VD_4);

	writel(0, vtg->regs + VTG_TOP_V_HD_4);

	writel(0, vtg->regs + VTG_BOT_V_HD_4);



	/* mode */

	/* mode */

	writel(type, vtg->regs + VTG_MODE);

	writel(type, vtg->regs + VTG_MODE);

}

}