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Commit 7e8d9415 authored by Sebastian Hesselbarth's avatar Sebastian Hesselbarth Committed by Jason Cooper
Browse files

pinctrl: mvebu: pinctrl driver core



This patch adds a pinctrl driver core for Marvell SoCs plus DT
binding documentation. This core driver will be used by SoC family
specific drivers, i.e. Armada XP, Armada 370, Dove, Kirkwood, aso.

Signed-off-by: default avatarSebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: default avatarThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: default avatarStephen Warren <swarren@wwwdotorg.org>
Signed-off-by: default avatarJason Cooper <jason@lakedaemon.net>

Conflicts:

	arch/arm/Kconfig
parent 5b40baee
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* Marvell SoC pinctrl core driver for mpp

The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
(mpp) to a specific function. For each SoC family there is a SoC specific
driver using this core driver.

Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices, including the meaning of the
phrase "pin configuration node".

A Marvell SoC pin configuration node is a node of a group of pins which can
be used for a specific device or function. Each node requires one or more
mpp pins or group of pins and a mpp function common to all pins.

Required properties for pinctrl driver:
- compatible: "marvell,<soc>-pinctrl"
  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.

Required properties for pin configuration node:
- marvell,pins: string array of mpp pins or group of pins to be muxed.
- marvell,function: string representing a function to mux to for all
    marvell,pins given in this pin configuration node. The function has to be
    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
    valid pin/pin group names and available function names for each SoC.

Examples:

uart1: serial@12100 {
	compatible = "ns16550a";
	reg = <0x12100 0x100>;
	reg-shift = <2>;
	interrupts = <7>;

	pinctrl-0 = <&pmx_uart1_sw>;
	pinctrl-names = "default";
};

pinctrl: pinctrl@d0200 {
	compatible = "marvell,dove-pinctrl";
	reg = <0xd0200 0x20>;

	pmx_uart1_sw: pmx-uart1-sw {
		marvell,pins = "mpp_uart1";
		marvell,function = "uart1";
	};
};
+1 −0
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@@ -568,6 +568,7 @@ config ARCH_MVEBU
	select IRQ_DOMAIN
	select COMMON_CLK
	select PLAT_ORION
	select PINCTRL
	help
	  Support for the Marvell SoC Family with device tree support

+6 −0
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@@ -145,6 +145,12 @@ config PINCTRL_COH901
	  COH 901 335 and COH 901 571/3. They contain 3, 5 or 7
	  ports of 8 GPIO pins each.

config PINCTRL_MVEBU
	bool
	depends on ARCH_MVEBU
	select PINMUX
	select PINCONF

source "drivers/pinctrl/spear/Kconfig"

endmenu
+1 −0
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@@ -29,5 +29,6 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
obj-$(CONFIG_PINCTRL_TEGRA30)	+= pinctrl-tegra30.o
obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
obj-$(CONFIG_PINCTRL_COH901)	+= pinctrl-coh901.o
obj-$(CONFIG_PINCTRL_MVEBU)	+= pinctrl-mvebu.o

obj-$(CONFIG_PLAT_SPEAR)	+= spear/
+754 −0

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