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Commit 7e6d8f83 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch '4.14-fixes' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS fixes from Ralf Baechle:

 - Fix a build error on MSP71xx which used to rely on somehow magically
   <asm/setup.h> being pulled in which no longer happens.

 - Fix the __write_64bit_c0_split inline assembler where there was the
   theoretical possibility of GCC interpret the constraints such that
   bad code could result.

 - A __init was causing section mismatch errors on Alchemy. Just to be
   on the safe side, Manuel's patch does away with all of them.

 - Fix perf event init.

* '4.14-fixes' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus:
  MIPS: PCI: fix pcibios_map_irq section mismatch
  MIPS: Fix input modify in __write_64bit_c0_split()
  MIPS: MSP71xx: Include asm/setup.h
  MIPS: Fix perf event init
parents c8107ed9 8eba3651

arch/mips/include/asm/mipsregs.h

+9 −6
Original line number Diff line number Diff line
@@ -1377,29 +1377,32 @@ do { \ 


#define __write_64bit_c0_split(source, sel, val)			\

do {									\

	unsigned long long __tmp;					\

	unsigned long __flags;						\

									\

	local_irq_save(__flags);					\

	if (sel == 0)							\

		__asm__ __volatile__(					\

			".set\tmips64\n\t"				\

			"dsll\t%L0, %L0, 32\n\t"			\

			"dsll\t%L0, %L1, 32\n\t"			\

			"dsrl\t%L0, %L0, 32\n\t"			\

			"dsll\t%M0, %M0, 32\n\t"			\

			"dsll\t%M0, %M1, 32\n\t"			\

			"or\t%L0, %L0, %M0\n\t"				\

			"dmtc0\t%L0, " #source "\n\t"			\

			".set\tmips0"					\

			: : "r" (val));					\

			: "=&r,r" (__tmp)				\

			: "r,0" (val));					\

	else								\

		__asm__ __volatile__(					\

			".set\tmips64\n\t"				\

			"dsll\t%L0, %L0, 32\n\t"			\

			"dsll\t%L0, %L1, 32\n\t"			\

			"dsrl\t%L0, %L0, 32\n\t"			\

			"dsll\t%M0, %M0, 32\n\t"			\

			"dsll\t%M0, %M1, 32\n\t"			\

			"or\t%L0, %L0, %M0\n\t"				\

			"dmtc0\t%L0, " #source ", " #sel "\n\t"		\

			".set\tmips0"					\

			: : "r" (val));					\

			: "=&r,r" (__tmp)				\

			: "r,0" (val));					\

	local_irq_restore(__flags);					\

} while (0)

arch/mips/kernel/perf_event_mipsxx.c

+1 −2
Original line number Diff line number Diff line
@@ -618,8 +618,7 @@ static int mipspmu_event_init(struct perf_event *event) 
		return -ENOENT;

	}



	if ((unsigned int)event->cpu >= nr_cpumask_bits ||

	    (event->cpu >= 0 && !cpu_online(event->cpu)))

	if (event->cpu >= 0 && !cpu_online(event->cpu))

		return -ENODEV;



	if (!atomic_inc_not_zero(&active_events)) {

arch/mips/pci/fixup-capcella.c

+1 −1
Original line number Diff line number Diff line
@@ -38,7 +38,7 @@ static char irq_tab_capcella[][5] __initdata = { 
 [14] = { -1, INTA, INTB, INTC, INTD }

};



int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	return irq_tab_capcella[slot][pin];

}

arch/mips/pci/fixup-cobalt.c

+1 −1
Original line number Diff line number Diff line
@@ -174,7 +174,7 @@ static char irq_tab_raq2[] __initdata = { 
  [COBALT_PCICONF_ETH1]	   = ETH1_IRQ

};



int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	if (cobalt_board_id <= COBALT_BRD_ID_QUBE1)

		return irq_tab_qube1[slot];

arch/mips/pci/fixup-emma2rh.c

+1 −1
Original line number Diff line number Diff line
@@ -85,7 +85,7 @@ static void emma2rh_pci_host_fixup(struct pci_dev *dev) 
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH,

			 emma2rh_pci_host_fixup);



int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)

{

	return irq_map[slot][pin];

}