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Commit 7dfa2b2c authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
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ARM: dts: msm: Add control register configurations for ACD v2 

For each power level, configure control register values which hold
DVM margins for Adaptive Clock Distribution feature.

Change-Id: I684942c91c93cbfe7fb13ad678b2477579bf8237
parent e000a932

qcom/kona-v2-gpu.dtsi

+10 −0
Original line number Diff line number Diff line
@@ -60,6 +60,8 @@ 
			qcom,bus-freq-ddr8 = <8>;

			qcom,bus-min-ddr8 = <8>;

			qcom,bus-max-ddr8 = <11>;



			qcom,acd-level = <0x802b5ffd>;

		};



		qcom,gpu-pwrlevel@1 {
@@ -72,6 +74,8 @@ 
			qcom,bus-freq-ddr8 = <8>;

			qcom,bus-min-ddr8 = <7>;

			qcom,bus-max-ddr8 = <9>;



			qcom,acd-level = <0xa02b5ffd>;

		};



		qcom,gpu-pwrlevel@2 {
@@ -84,6 +88,8 @@ 
			qcom,bus-freq-ddr8 = <8>;

			qcom,bus-min-ddr8 = <7>;

			qcom,bus-max-ddr8 = <9>;



			qcom,acd-level = <0xa02b5ffd>;

		};



		qcom,gpu-pwrlevel@3 {
@@ -96,6 +102,8 @@ 
			qcom,bus-freq-ddr8 = <8>;

			qcom,bus-min-ddr8 = <6>;

			qcom,bus-max-ddr8 = <9>;



			qcom,acd-level = <0xa02b5ffd>;

		};



		qcom,gpu-pwrlevel@4 {
@@ -108,6 +116,8 @@ 
			qcom,bus-freq-ddr8 = <6>;

			qcom,bus-min-ddr8 = <4>;

			qcom,bus-max-ddr8 = <9>;



			qcom,acd-level = <0xa02b5ffd>;

		};



		qcom,gpu-pwrlevel@5 {