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Commit 7dfa2b2c authored by Mohammed Mirza Mandayappurath Manzoor's avatar Mohammed Mirza Mandayappurath Manzoor
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ARM: dts: msm: Add control register configurations for ACD v2 

For each power level, configure control register values which hold
DVM margins for Adaptive Clock Distribution feature.

Change-Id: I684942c91c93cbfe7fb13ad678b2477579bf8237
parent e000a932
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