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Commit 7d64ac64 authored by Aravind Gopalakrishnan's avatar Aravind Gopalakrishnan Committed by Borislav Petkov
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x86, amd_nb: Clarify F15h, model 30h GART and L3 support 



F15h, models 0x30 and later don't have a GART. Note that. Also check
CPUID leaf 0x80000006 for L3 prescence because there are models which
don't sport an L3 cache.

Signed-off-by: default avatarAravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
[ Boris: rewrite commit message, cleanup comments. ]
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
parent 6bdaa63c

arch/x86/kernel/amd_nb.c

+11 −2
Original line number Original line Diff line number Diff line
@@ -20,6 +20,7 @@ const struct pci_device_id amd_nb_misc_ids[] = { 
	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M10H_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F3) },

	{}

	{}

};

};
@@ -27,6 +28,7 @@ EXPORT_SYMBOL(amd_nb_misc_ids); 




static const struct pci_device_id amd_nb_link_ids[] = {

static const struct pci_device_id amd_nb_link_ids[] = {

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_15H_M30H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },

	{ PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_16H_NB_F4) },

	{}

	{}

};

};
@@ -83,10 +85,17 @@ int amd_cache_northbridges(void) 
			next_northbridge(link, amd_nb_link_ids);

			next_northbridge(link, amd_nb_link_ids);

	}

	}





	/* GART present only on Fam15h upto model 0fh */

	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||

	if (boot_cpu_data.x86 == 0xf || boot_cpu_data.x86 == 0x10 ||

	    boot_cpu_data.x86 == 0x15)

	    (boot_cpu_data.x86 == 0x15 && boot_cpu_data.x86_model < 0x10))

		amd_northbridges.flags |= AMD_NB_GART;

		amd_northbridges.flags |= AMD_NB_GART;





	/*

	 * Check for L3 cache presence.

	 */

	if (!cpuid_edx(0x80000006))

		return 0;



	/*

	/*

	 * Some CPU families support L3 Cache Index Disable. There are some

	 * Some CPU families support L3 Cache Index Disable. There are some

	 * limitations because of E382 and E388 on family 0x10.

	 * limitations because of E382 and E388 on family 0x10.