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Commit 7d5a603a authored by RAJAT GUPTA's avatar RAJAT GUPTA Committed by Gerrit - the friendly Code Review server
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disp: pll: update clk names for lagoon target 



Update clocks names for lagoon target according to clock
plan.

Change-Id: Ibc798a31d4234e4d6925ba9add2bb0ddb55909bc
Signed-off-by: default avatarRAJAT GUPTA <rajatgu@codeaurora.org>
parent d92ce846

pll/dp_pll_10nm.c

+9 −9
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 */



/*
@@ -100,12 +100,12 @@ static struct dp_pll_vco_clk dp_vco_clk = { 
	},

};



static struct clk_fixed_factor dp_link_clk_divsel_ten = {

static struct clk_fixed_factor dp_phy_pll_link_clk = {

	.div = 10,

	.mult = 1,



	.hw.init = &(struct clk_init_data){

		.name = "dp_link_clk_divsel_ten",

		.name = "dp_phy_pll_link_clk",

		.parent_names =

			(const char *[]){ "dp_vco_clk" },

		.num_parents = 1,
@@ -199,14 +199,14 @@ static unsigned long mux_recalc_rate(struct clk_hw *hw, 
		return (vco->rate / 2);

}



static struct clk_regmap_mux dp_vco_divided_clk_src_mux = {

static struct clk_regmap_mux dp_phy_pll_vco_div_clk = {

	.reg = 0x64,

	.shift = 0,

	.width = 2,



	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "dp_vco_divided_clk_src_mux",

			.name = "dp_phy_pll_vco_div_clk",

			.parent_names =

				(const char *[]){"dp_vco_divsel_two_clk_src",

					"dp_vco_divsel_four_clk_src",
@@ -220,11 +220,11 @@ static struct clk_regmap_mux dp_vco_divided_clk_src_mux = { 


static struct clk_hw *mdss_dp_pllcc_10nm[] = {

	[DP_VCO_CLK] = &dp_vco_clk.hw,

	[DP_LINK_CLK_DIVSEL_TEN] = &dp_link_clk_divsel_ten.hw,

	[DP_PHY_PLL_LINK_CLK] = &dp_phy_pll_link_clk.hw,

	[DP_VCO_DIVIDED_TWO_CLK_SRC] = &dp_vco_divsel_two_clk_src.hw,

	[DP_VCO_DIVIDED_FOUR_CLK_SRC] = &dp_vco_divsel_four_clk_src.hw,

	[DP_VCO_DIVIDED_SIX_CLK_SRC] = &dp_vco_divsel_six_clk_src.hw,

	[DP_VCO_DIVIDED_CLK_SRC_MUX] = &dp_vco_divided_clk_src_mux.clkr.hw,

	[DP_PHY_PLL_VCO_DIV_CLK] = &dp_phy_pll_vco_div_clk.clkr.hw,

};



int dp_pll_clock_register_10nm(struct platform_device *pdev,
@@ -253,14 +253,14 @@ int dp_pll_clock_register_10nm(struct platform_device *pdev, 
	/* Set client data for vco, mux and div clocks */

	regmap = devm_regmap_init(&pdev->dev, &dp_pixel_mux_regmap_ops,

			pll_res, &dp_pll_10nm_cfg);

	dp_vco_divided_clk_src_mux.clkr.regmap = regmap;

	dp_phy_pll_vco_div_clk.clkr.regmap = regmap;

	mux_clk_ops = clk_regmap_mux_closest_ops;

	mux_clk_ops.determine_rate = clk_mux_determine_rate;

	mux_clk_ops.recalc_rate = mux_recalc_rate;



	dp_vco_clk.priv = pll_res;



	for (i = DP_VCO_CLK; i <= DP_VCO_DIVIDED_CLK_SRC_MUX; i++) {

	for (i = DP_VCO_CLK; i <= DP_PHY_PLL_VCO_DIV_CLK; i++) {

		pr_debug("reg clk: %d index: %d\n", i, pll_res->index);

		clk = devm_clk_register(&pdev->dev,

				mdss_dp_pllcc_10nm[i]);