Merge "clk: qcom: bengal: Add ufs clkref clock for GCC" (7d456b7a) · Commits · e / devices / android_kernel_fairphone_FP4

drivers/clk/qcom/gcc-bengal.c

+14 −0

Original line number	Diff line number	Diff line
		@@ -3275,6 +3275,19 @@ static struct clk_branch gcc_sys_noc_usb3_prim_axi_clk = {
		},
		};

		static struct clk_branch gcc_ufs_clkref_clk = {
		.halt_reg = 0x8c000,
		.halt_check = BRANCH_HALT,
		.clkr = {
		.enable_reg = 0x8c000,
		.enable_mask = BIT(0),
		.hw.init = &(struct clk_init_data){
		.name = "gcc_ufs_clkref_clk",
		.ops = &clk_branch2_ops,
		},
		},
		};

		static struct clk_branch gcc_ufs_phy_ahb_clk = {
		.halt_reg = 0x45014,
		.halt_check = BRANCH_HALT,
		@@ -3744,6 +3757,7 @@ static struct clk_regmap *gcc_bengal_clocks[] = {
		[GCC_SYS_NOC_CPUSS_AHB_CLK] = &gcc_sys_noc_cpuss_ahb_clk.clkr,
		[GCC_SYS_NOC_UFS_PHY_AXI_CLK] = &gcc_sys_noc_ufs_phy_axi_clk.clkr,
		[GCC_SYS_NOC_USB3_PRIM_AXI_CLK] = &gcc_sys_noc_usb3_prim_axi_clk.clkr,
		[GCC_UFS_CLKREF_CLK] = &gcc_ufs_clkref_clk.clkr,
		[GCC_UFS_PHY_AHB_CLK] = &gcc_ufs_phy_ahb_clk.clkr,
		[GCC_UFS_PHY_AXI_CLK] = &gcc_ufs_phy_axi_clk.clkr,
		[GCC_UFS_PHY_AXI_CLK_SRC] = &gcc_ufs_phy_axi_clk_src.clkr,

+2 −2

Original line number	Diff line number	Diff line
		@@ -53,7 +53,7 @@ static const char * const gpu_cc_parent_names_0[] = {
		"bi_tcxo",
		"gpu_cc_pll0_out_main",
		"gpu_cc_pll1_out_main",
		"gpll0_out_main",
		"gpll0",
		"gpll0_out_main_div",
		"core_bi_pll_test_se",
		};
		@@ -74,7 +74,7 @@ static const char * const gpu_cc_parent_names_1[] = {
		"gpu_cc_pll0_out_aux2",
		"gpu_cc_pll1_out_aux",
		"gpu_cc_pll1_out_aux2",
		"gpll0_out_main",
		"gpll0",
		"core_bi_pll_test_se",
		};

+1 −0