Commit 7cef0c7b authored Jul 21, 2020 by Hareesh Gundu

msm: kgsl Update GPU to DDR bus-width for A702



For A702 GPU to DDR bus width is 128bit, Hence update
bus-width configuration to reflect correct status.

Change-Id: Ic5b918434c63f71c412f782564e7a7aa818da6f5
Signed-off-by: Hareesh Gundu <hareeshg@codeaurora.org>

parent 51d808aa

drivers/gpu/msm/adreno-gpulist.h

+1 −1

Original line number	Diff line number	Diff line
		@@ -1464,7 +1464,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a702 = {
		.gpudev = &adreno_a6xx_gpudev,
		.gmem_size = SZ_128K,
		.busy_mask = 0xfffffffe,
		.bus_width = 32,
		.bus_width = 16,
		},
		.prim_fifo_threshold = 0x0000c000,
		.sqefw_name = "a702_sqe.fw",