Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 7cb9cf02 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu 

Pull m68knommu arch updates from Greg Ungerer:
 "Most of it is a cleanup of the ColdFire hardware header files.  We
  have had a few occurrances of bugs caused by inconsistent definitions
  of peripheral addresses.  These patches make them all consistent, and
  also clean out a bunch of old crap.  Overall we remove about 1000
  lines."

* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu: (27 commits)
  m68knommu: fix inconsistent formating in ColdFire 5407 definitions
  m68knommu: fix inconsistent formating in ColdFire 5307 definitions
  m68knommu: fix inconsistent formating in ColdFire 527x definitions
  m68knommu: fix inconsistent formating in ColdFire 5272 definitions
  m68knommu: fix inconsistent formating in ColdFire 523x definitions
  m68knommu: clean up ColdFire 54xx General Timer definitions
  m68knommu: clean up Pin Assignment definitions for the 54xx ColdFire CPU
  m68knommu: fix multi-function pin setup for FEC module on ColdFire 523x
  m68knommu: move ColdFire slice timer address defiens to 54xx header
  m68knommu: use read/write IO access functions in ColdFire m532x setup code
  m68knommu: modify ColdFire 532x GPIO register definitions to be consistent
  m68knommu: remove a lot of unsed definitions for 532x ColdFire
  m68knommu: use definitions for the ColdFire 528x FEC multi-function pins
  m68knommu: remove address offsets relative to IPSBAR for ColdFire 527x
  m68knommu: remove unused ColdFire 5282 register definitions
  m68knommu: fix wrong register offsets used for ColdFire 5272 multi-function pins
  m68knommu: make ColdFire 5249 MBAR2 register definitions absolute addresses
  m68knommu: make remaining ColdFire 5272 register definitions absolute addresses
  m68knommu: make ColdFire Park and Assignment register definitions absolute addresses
  m68knommu: make ColdFire Chip Select register definitions absolute addresses
  ...
parents dc92b1f9 a2551728

arch/m68k/include/asm/cacheflush_no.h

+8 −11
Original line number Diff line number Diff line
@@ -34,10 +34,9 @@ static inline void __clear_cache_all(void) 
{

#ifdef CACHE_INVALIDATE

	__asm__ __volatile__ (

		"movel	%0, %%d0\n\t"

		"movec	%%d0, %%CACR\n\t"

		"movec	%0, %%CACR\n\t"

		"nop\n\t"

		: : "i" (CACHE_INVALIDATE) : "d0" );

		: : "r" (CACHE_INVALIDATE) );

#endif

}
@@ -58,10 +57,9 @@ static inline void __flush_icache_all(void) 
{

#ifdef CACHE_INVALIDATEI

	__asm__ __volatile__ (

		"movel	%0, %%d0\n\t"

		"movec	%%d0, %%CACR\n\t"

		"movec	%0, %%CACR\n\t"

		"nop\n\t"

		: : "i" (CACHE_INVALIDATEI) : "d0" );

		: : "r" (CACHE_INVALIDATEI) );

#endif

}
@@ -72,19 +70,18 @@ static inline void __flush_dcache_all(void) 
#endif

#ifdef CACHE_INVALIDATED

	__asm__ __volatile__ (

		"movel	%0, %%d0\n\t"

		"movec	%%d0, %%CACR\n\t"

		"movec	%0, %%CACR\n\t"

		"nop\n\t"

		: : "i" (CACHE_INVALIDATED) : "d0" );

		: : "r" (CACHE_INVALIDATED) );

#else

	/* Flush the wrtite buffer */

	/* Flush the write buffer */

	__asm__ __volatile__ ( "nop" );

#endif

}



/*

 * Push cache entries at supplied address. We want to write back any dirty

 * data and the invalidate the cache lines associated with this address.

 * data and then invalidate the cache lines associated with this address.

 */

static inline void cache_push(unsigned long paddr, int len)

{

arch/m68k/include/asm/m5206sim.h

+49 −49
Original line number Diff line number Diff line
@@ -21,33 +21,33 @@ 
/*

 *	Define the 5206 SIM register set addresses.

 */

#define	MCFSIM_SIMR		0x03		/* SIM Config reg (r/w) */

#define	MCFSIM_ICR1		0x14		/* Intr Ctrl reg 1 (r/w) */

#define	MCFSIM_ICR2		0x15		/* Intr Ctrl reg 2 (r/w) */

#define	MCFSIM_ICR3		0x16		/* Intr Ctrl reg 3 (r/w) */

#define	MCFSIM_ICR4		0x17		/* Intr Ctrl reg 4 (r/w) */

#define	MCFSIM_ICR5		0x18		/* Intr Ctrl reg 5 (r/w) */

#define	MCFSIM_ICR6		0x19		/* Intr Ctrl reg 6 (r/w) */

#define	MCFSIM_ICR7		0x1a		/* Intr Ctrl reg 7 (r/w) */

#define	MCFSIM_ICR8		0x1b		/* Intr Ctrl reg 8 (r/w) */

#define	MCFSIM_ICR9		0x1c		/* Intr Ctrl reg 9 (r/w) */

#define	MCFSIM_ICR10		0x1d		/* Intr Ctrl reg 10 (r/w) */

#define	MCFSIM_ICR11		0x1e		/* Intr Ctrl reg 11 (r/w) */

#define	MCFSIM_ICR12		0x1f		/* Intr Ctrl reg 12 (r/w) */

#define	MCFSIM_ICR13		0x20		/* Intr Ctrl reg 13 (r/w) */

#define	MCFSIM_SIMR		(MCF_MBAR + 0x03)	/* SIM Config reg */

#define	MCFSIM_ICR1		(MCF_MBAR + 0x14)	/* Intr Ctrl reg 1 */

#define	MCFSIM_ICR2		(MCF_MBAR + 0x15)	/* Intr Ctrl reg 2 */

#define	MCFSIM_ICR3		(MCF_MBAR + 0x16)	/* Intr Ctrl reg 3 */

#define	MCFSIM_ICR4		(MCF_MBAR + 0x17)	/* Intr Ctrl reg 4 */

#define	MCFSIM_ICR5		(MCF_MBAR + 0x18)	/* Intr Ctrl reg 5 */

#define	MCFSIM_ICR6		(MCF_MBAR + 0x19)	/* Intr Ctrl reg 6 */

#define	MCFSIM_ICR7		(MCF_MBAR + 0x1a)	/* Intr Ctrl reg 7 */

#define	MCFSIM_ICR8		(MCF_MBAR + 0x1b)	/* Intr Ctrl reg 8 */

#define	MCFSIM_ICR9		(MCF_MBAR + 0x1c)	/* Intr Ctrl reg 9 */

#define	MCFSIM_ICR10		(MCF_MBAR + 0x1d)	/* Intr Ctrl reg 10 */

#define	MCFSIM_ICR11		(MCF_MBAR + 0x1e)	/* Intr Ctrl reg 11 */

#define	MCFSIM_ICR12		(MCF_MBAR + 0x1f)	/* Intr Ctrl reg 12 */

#define	MCFSIM_ICR13		(MCF_MBAR + 0x20)	/* Intr Ctrl reg 13 */

#ifdef CONFIG_M5206e

#define	MCFSIM_ICR14		0x21		/* Intr Ctrl reg 14 (r/w) */

#define	MCFSIM_ICR15		0x22		/* Intr Ctrl reg 15 (r/w) */

#define	MCFSIM_ICR14		(MCF_MBAR + 0x21)	/* Intr Ctrl reg 14 */

#define	MCFSIM_ICR15		(MCF_MBAR + 0x22)	/* Intr Ctrl reg 15 */

#endif



#define MCFSIM_IMR		0x36		/* Interrupt Mask reg (r/w) */

#define MCFSIM_IPR		0x3a		/* Interrupt Pend reg (r/w) */

#define	MCFSIM_IMR		(MCF_MBAR + 0x36)	/* Interrupt Mask */

#define	MCFSIM_IPR		(MCF_MBAR + 0x3a)	/* Interrupt Pending */



#define	MCFSIM_RSR		0x40		/* Reset Status reg (r/w) */

#define	MCFSIM_SYPCR		0x41		/* System Protection reg (r/w)*/

#define	MCFSIM_RSR		(MCF_MBAR + 0x40)	/* Reset Status */

#define	MCFSIM_SYPCR		(MCF_MBAR + 0x41)	/* System Protection */



#define	MCFSIM_SWIVR		0x42		/* SW Watchdog intr reg (r/w) */

#define	MCFSIM_SWSR		0x43		/* SW Watchdog service (r/w) */

#define	MCFSIM_SWIVR		(MCF_MBAR + 0x42)	/* SW Watchdog intr */

#define	MCFSIM_SWSR		(MCF_MBAR + 0x43)	/* SW Watchdog srv */



#define	MCFSIM_DCRR		(MCF_MBAR + 0x46) /* DRAM Refresh reg (r/w) */

#define	MCFSIM_DCTR		(MCF_MBAR + 0x4a) /* DRAM Timing reg (r/w) */
@@ -58,36 +58,36 @@ 
#define	MCFSIM_DMR1		(MCF_MBAR + 0x5c) /* DRAM 1 Mask reg (r/w) */

#define	MCFSIM_DCR1		(MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */



#define	MCFSIM_CSAR0		0x64		/* CS 0 Address 0 reg (r/w) */

#define	MCFSIM_CSMR0		0x68		/* CS 0 Mask 0 reg (r/w) */

#define	MCFSIM_CSCR0		0x6e		/* CS 0 Control reg (r/w) */

#define	MCFSIM_CSAR1		0x70		/* CS 1 Address reg (r/w) */

#define	MCFSIM_CSMR1		0x74		/* CS 1 Mask reg (r/w) */

#define	MCFSIM_CSCR1		0x7a		/* CS 1 Control reg (r/w) */

#define	MCFSIM_CSAR2		0x7c		/* CS 2 Address reg (r/w) */

#define	MCFSIM_CSMR2		0x80		/* CS 2 Mask reg (r/w) */

#define	MCFSIM_CSCR2		0x86		/* CS 2 Control reg (r/w) */

#define	MCFSIM_CSAR3		0x88		/* CS 3 Address reg (r/w) */

#define	MCFSIM_CSMR3		0x8c		/* CS 3 Mask reg (r/w) */

#define	MCFSIM_CSCR3		0x92		/* CS 3 Control reg (r/w) */

#define	MCFSIM_CSAR4		0x94		/* CS 4 Address reg (r/w) */

#define	MCFSIM_CSMR4		0x98		/* CS 4 Mask reg (r/w) */

#define	MCFSIM_CSCR4		0x9e		/* CS 4 Control reg (r/w) */

#define	MCFSIM_CSAR5		0xa0		/* CS 5 Address reg (r/w) */

#define	MCFSIM_CSMR5		0xa4		/* CS 5 Mask reg (r/w) */

#define	MCFSIM_CSCR5		0xaa		/* CS 5 Control reg (r/w) */

#define	MCFSIM_CSAR6		0xac		/* CS 6 Address reg (r/w) */

#define	MCFSIM_CSMR6		0xb0		/* CS 6 Mask reg (r/w) */

#define	MCFSIM_CSCR6		0xb6		/* CS 6 Control reg (r/w) */

#define	MCFSIM_CSAR7		0xb8		/* CS 7 Address reg (r/w) */

#define	MCFSIM_CSMR7		0xbc		/* CS 7 Mask reg (r/w) */

#define	MCFSIM_CSCR7		0xc2		/* CS 7 Control reg (r/w) */

#define	MCFSIM_DMCR		0xc6		/* Default control */

#define	MCFSIM_CSAR0		(MCF_MBAR + 0x64)	/* CS 0 Address reg */

#define	MCFSIM_CSMR0		(MCF_MBAR + 0x68)	/* CS 0 Mask reg */

#define	MCFSIM_CSCR0		(MCF_MBAR + 0x6e)	/* CS 0 Control reg */

#define	MCFSIM_CSAR1		(MCF_MBAR + 0x70)	/* CS 1 Address reg */

#define	MCFSIM_CSMR1		(MCF_MBAR + 0x74)	/* CS 1 Mask reg */

#define	MCFSIM_CSCR1		(MCF_MBAR + 0x7a)	/* CS 1 Control reg */

#define	MCFSIM_CSAR2		(MCF_MBAR + 0x7c)	/* CS 2 Address reg */

#define	MCFSIM_CSMR2		(MCF_MBAR + 0x80)	/* CS 2 Mask reg */

#define	MCFSIM_CSCR2		(MCF_MBAR + 0x86)	/* CS 2 Control reg */

#define	MCFSIM_CSAR3		(MCF_MBAR + 0x88)	/* CS 3 Address reg */

#define	MCFSIM_CSMR3		(MCF_MBAR + 0x8c)	/* CS 3 Mask reg */

#define	MCFSIM_CSCR3		(MCF_MBAR + 0x92)	/* CS 3 Control reg */

#define	MCFSIM_CSAR4		(MCF_MBAR + 0x94)	/* CS 4 Address reg */

#define	MCFSIM_CSMR4		(MCF_MBAR + 0x98)	/* CS 4 Mask reg */

#define	MCFSIM_CSCR4		(MCF_MBAR + 0x9e)	/* CS 4 Control reg */

#define	MCFSIM_CSAR5		(MCF_MBAR + 0xa0)	/* CS 5 Address reg */

#define	MCFSIM_CSMR5		(MCF_MBAR + 0xa4)	/* CS 5 Mask reg */

#define	MCFSIM_CSCR5		(MCF_MBAR + 0xaa)	/* CS 5 Control reg */

#define	MCFSIM_CSAR6		(MCF_MBAR + 0xac)	/* CS 6 Address reg */

#define	MCFSIM_CSMR6		(MCF_MBAR + 0xb0)	/* CS 6 Mask reg */

#define	MCFSIM_CSCR6		(MCF_MBAR + 0xb6)	/* CS 6 Control reg */

#define	MCFSIM_CSAR7		(MCF_MBAR + 0xb8)	/* CS 7 Address reg */

#define	MCFSIM_CSMR7		(MCF_MBAR + 0xbc)	/* CS 7 Mask reg */

#define	MCFSIM_CSCR7		(MCF_MBAR + 0xc2)	/* CS 7 Control reg */

#define	MCFSIM_DMCR		(MCF_MBAR + 0xc6)	/* Default control */



#ifdef CONFIG_M5206e

#define	MCFSIM_PAR		0xca		/* Pin Assignment reg (r/w) */

#define	MCFSIM_PAR		(MCF_MBAR + 0xca)	/* Pin Assignment */

#else

#define	MCFSIM_PAR		0xcb		/* Pin Assignment reg (r/w) */

#define	MCFSIM_PAR		(MCF_MBAR + 0xcb)	/* Pin Assignment */

#endif



#define	MCFTIMER_BASE1		(MCF_MBAR + 0x100)	/* Base of TIMER1 */

arch/m68k/include/asm/m523xsim.h

+16 −8
Original line number Diff line number Diff line
@@ -189,8 +189,16 @@ 
/*

 * Pin Assignment

*/

#define	MCFGPIO_PAR_AD		(MCF_IPSBAR + 0x100040)

#define	MCFGPIO_PAR_BUSCTL	(MCF_IPSBAR + 0x100042)

#define	MCFGPIO_PAR_BS		(MCF_IPSBAR + 0x100044)

#define	MCFGPIO_PAR_CS		(MCF_IPSBAR + 0x100045)

#define	MCFGPIO_PAR_SDRAM	(MCF_IPSBAR + 0x100046)

#define	MCFGPIO_PAR_FECI2C	(MCF_IPSBAR + 0x100047)

#define	MCFGPIO_PAR_UART	(MCF_IPSBAR + 0x100048)

#define	MCFGPIO_PAR_QSPI	(MCF_IPSBAR + 0x10004A)

#define	MCFGPIO_PAR_TIMER	(MCF_IPSBAR + 0x10004C)

#define	MCFGPIO_PAR_ETPU	(MCF_IPSBAR + 0x10004E)



/*

 * DMA unit base addresses.

arch/m68k/include/asm/m5249sim.h

+49 −49
Original line number Diff line number Diff line
@@ -25,41 +25,41 @@ 
/*

 *	Define the 5249 SIM register set addresses.

 */

#define	MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */

#define	MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/

#define	MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */

#define	MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */

#define	MCFSIM_PAR		0x04		/* Pin Assignment reg (r/w) */

#define	MCFSIM_IRQPAR		0x06		/* Interrupt Assignment reg (r/w) */

#define	MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/

#define	MCFSIM_IPR		0x40		/* Interrupt Pend reg (r/w) */

#define	MCFSIM_IMR		0x44		/* Interrupt Mask reg (r/w) */

#define	MCFSIM_AVR		0x4b		/* Autovector Ctrl reg (r/w) */

#define	MCFSIM_ICR0		0x4c		/* Intr Ctrl reg 0 (r/w) */

#define	MCFSIM_ICR1		0x4d		/* Intr Ctrl reg 1 (r/w) */

#define	MCFSIM_ICR2		0x4e		/* Intr Ctrl reg 2 (r/w) */

#define	MCFSIM_ICR3		0x4f		/* Intr Ctrl reg 3 (r/w) */

#define	MCFSIM_ICR4		0x50		/* Intr Ctrl reg 4 (r/w) */

#define	MCFSIM_ICR5		0x51		/* Intr Ctrl reg 5 (r/w) */

#define	MCFSIM_ICR6		0x52		/* Intr Ctrl reg 6 (r/w) */

#define	MCFSIM_ICR7		0x53		/* Intr Ctrl reg 7 (r/w) */

#define	MCFSIM_ICR8		0x54		/* Intr Ctrl reg 8 (r/w) */

#define	MCFSIM_ICR9		0x55		/* Intr Ctrl reg 9 (r/w) */

#define	MCFSIM_ICR10		0x56		/* Intr Ctrl reg 10 (r/w) */

#define	MCFSIM_ICR11		0x57		/* Intr Ctrl reg 11 (r/w) */



#define MCFSIM_CSAR0		0x80		/* CS 0 Address 0 reg (r/w) */

#define MCFSIM_CSMR0		0x84		/* CS 0 Mask 0 reg (r/w) */

#define MCFSIM_CSCR0		0x8a		/* CS 0 Control reg (r/w) */

#define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */

#define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */

#define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */

#define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */

#define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */

#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */

#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */

#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */

#define	MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */

#define	MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */

#define	MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */

#define	MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */

#define	MCFSIM_PAR		(MCF_MBAR + 0x04)	/* Pin Assignment */

#define	MCFSIM_IRQPAR		(MCF_MBAR + 0x06)	/* Intr Assignment */

#define	MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */

#define	MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */

#define	MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */

#define	MCFSIM_AVR		(MCF_MBAR + 0x4b)	/* Autovector Ctrl */

#define	MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */

#define	MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */

#define	MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */

#define	MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */

#define	MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */

#define	MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */

#define	MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */

#define	MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */

#define	MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */

#define	MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */

#define	MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */

#define	MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */



#define	MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */

#define	MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */

#define	MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */

#define	MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */

#define	MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */

#define	MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */

#define	MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */

#define	MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */

#define	MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */

#define	MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */

#define	MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */

#define	MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */



#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */

#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */
@@ -134,23 +134,23 @@ 
#define	MCFSIM2_GPIO1ENABLE	(MCF_MBAR2 + 0x0B8)	/* GPIO1 enabled */

#define	MCFSIM2_GPIO1FUNC	(MCF_MBAR2 + 0x0BC)	/* GPIO1 function */



#define	MCFSIM2_GPIOINTSTAT	0xc0		/* GPIO interrupt status */

#define	MCFSIM2_GPIOINTCLEAR	0xc0		/* GPIO interrupt clear */

#define	MCFSIM2_GPIOINTENABLE	0xc4		/* GPIO interrupt enable */

#define	MCFSIM2_GPIOINTSTAT	(MCF_MBAR2 + 0xc0)	/* GPIO intr status */

#define	MCFSIM2_GPIOINTCLEAR	(MCF_MBAR2 + 0xc0)	/* GPIO intr clear */

#define	MCFSIM2_GPIOINTENABLE	(MCF_MBAR2 + 0xc4)	/* GPIO intr enable */



#define	MCFSIM2_INTLEVEL1	0x140		/* Interrupt level reg 1 */

#define	MCFSIM2_INTLEVEL2	0x144		/* Interrupt level reg 2 */

#define	MCFSIM2_INTLEVEL3	0x148		/* Interrupt level reg 3 */

#define	MCFSIM2_INTLEVEL4	0x14c		/* Interrupt level reg 4 */

#define	MCFSIM2_INTLEVEL5	0x150		/* Interrupt level reg 5 */

#define	MCFSIM2_INTLEVEL6	0x154		/* Interrupt level reg 6 */

#define	MCFSIM2_INTLEVEL7	0x158		/* Interrupt level reg 7 */

#define	MCFSIM2_INTLEVEL8	0x15c		/* Interrupt level reg 8 */

#define	MCFSIM2_INTLEVEL1	(MCF_MBAR2 + 0x140)	/* Intr level reg 1 */

#define	MCFSIM2_INTLEVEL2	(MCF_MBAR2 + 0x144)	/* Intr level reg 2 */

#define	MCFSIM2_INTLEVEL3	(MCF_MBAR2 + 0x148)	/* Intr level reg 3 */

#define	MCFSIM2_INTLEVEL4	(MCF_MBAR2 + 0x14c)	/* Intr level reg 4 */

#define	MCFSIM2_INTLEVEL5	(MCF_MBAR2 + 0x150)	/* Intr level reg 5 */

#define	MCFSIM2_INTLEVEL6	(MCF_MBAR2 + 0x154)	/* Intr level reg 6 */

#define	MCFSIM2_INTLEVEL7	(MCF_MBAR2 + 0x158)	/* Intr level reg 7 */

#define	MCFSIM2_INTLEVEL8	(MCF_MBAR2 + 0x15c)	/* Intr level reg 8 */



#define	MCFSIM2_DMAROUTE	0x188		/* DMA routing */

#define	MCFSIM2_DMAROUTE	(MCF_MBAR2 + 0x188)	/* DMA routing */



#define	MCFSIM2_IDECONFIG1	0x18c		/* IDEconfig1 */

#define	MCFSIM2_IDECONFIG2	0x190		/* IDEconfig2 */

#define	MCFSIM2_IDECONFIG1	(MCF_MBAR2 + 0x18c)	/* IDEconfig1 */

#define	MCFSIM2_IDECONFIG2	(MCF_MBAR2 + 0x190)	/* IDEconfig2 */



/*

 * Define the base interrupt for the second interrupt controller.

arch/m68k/include/asm/m525xsim.h

+35 −35
Original line number Diff line number Diff line
@@ -26,41 +26,41 @@ 
/*

 *	Define the 525x SIM register set addresses.

 */

#define MCFSIM_RSR		0x00		/* Reset Status reg (r/w) */

#define MCFSIM_SYPCR		0x01		/* System Protection reg (r/w)*/

#define MCFSIM_SWIVR		0x02		/* SW Watchdog intr reg (r/w) */

#define MCFSIM_SWSR		0x03		/* SW Watchdog service (r/w) */

#define MCFSIM_MPARK		0x0C		/* BUS Master Control Reg*/

#define MCFSIM_IPR		0x40		/* Interrupt Pend reg (r/w) */

#define MCFSIM_IMR		0x44		/* Interrupt Mask reg (r/w) */

#define MCFSIM_ICR0		0x4c		/* Intr Ctrl reg 0 (r/w) */

#define MCFSIM_ICR1		0x4d		/* Intr Ctrl reg 1 (r/w) */

#define MCFSIM_ICR2		0x4e		/* Intr Ctrl reg 2 (r/w) */

#define MCFSIM_ICR3		0x4f		/* Intr Ctrl reg 3 (r/w) */

#define MCFSIM_ICR4		0x50		/* Intr Ctrl reg 4 (r/w) */

#define MCFSIM_ICR5		0x51		/* Intr Ctrl reg 5 (r/w) */

#define MCFSIM_ICR6		0x52		/* Intr Ctrl reg 6 (r/w) */

#define MCFSIM_ICR7		0x53		/* Intr Ctrl reg 7 (r/w) */

#define MCFSIM_ICR8		0x54		/* Intr Ctrl reg 8 (r/w) */

#define MCFSIM_ICR9		0x55		/* Intr Ctrl reg 9 (r/w) */

#define MCFSIM_ICR10		0x56		/* Intr Ctrl reg 10 (r/w) */

#define MCFSIM_ICR11		0x57		/* Intr Ctrl reg 11 (r/w) */



#define MCFSIM_CSAR0		0x80		/* CS 0 Address 0 reg (r/w) */

#define MCFSIM_CSMR0		0x84		/* CS 0 Mask 0 reg (r/w) */

#define MCFSIM_CSCR0		0x8a		/* CS 0 Control reg (r/w) */

#define MCFSIM_CSAR1		0x8c		/* CS 1 Address reg (r/w) */

#define MCFSIM_CSMR1		0x90		/* CS 1 Mask reg (r/w) */

#define MCFSIM_CSCR1		0x96		/* CS 1 Control reg (r/w) */

#define MCFSIM_CSAR2		0x98		/* CS 2 Address reg (r/w) */

#define MCFSIM_CSMR2		0x9c		/* CS 2 Mask reg (r/w) */

#define MCFSIM_CSCR2		0xa2		/* CS 2 Control reg (r/w) */

#define MCFSIM_CSAR3		0xa4		/* CS 3 Address reg (r/w) */

#define MCFSIM_CSMR3		0xa8		/* CS 3 Mask reg (r/w) */

#define MCFSIM_CSCR3		0xae		/* CS 3 Control reg (r/w) */

#define MCFSIM_CSAR4		0xb0		/* CS 4 Address reg (r/w) */

#define MCFSIM_CSMR4		0xb4		/* CS 4 Mask reg (r/w) */

#define MCFSIM_CSCR4		0xba		/* CS 4 Control reg (r/w) */

#define MCFSIM_RSR		(MCF_MBAR + 0x00)	/* Reset Status */

#define MCFSIM_SYPCR		(MCF_MBAR + 0x01)	/* System Protection */

#define MCFSIM_SWIVR		(MCF_MBAR + 0x02)	/* SW Watchdog intr */

#define MCFSIM_SWSR		(MCF_MBAR + 0x03)	/* SW Watchdog srv */

#define MCFSIM_MPARK		(MCF_MBAR + 0x0C)	/* BUS Master Ctrl */

#define MCFSIM_IPR		(MCF_MBAR + 0x40)	/* Interrupt Pending */

#define MCFSIM_IMR		(MCF_MBAR + 0x44)	/* Interrupt Mask */

#define MCFSIM_ICR0		(MCF_MBAR + 0x4c)	/* Intr Ctrl reg 0 */

#define MCFSIM_ICR1		(MCF_MBAR + 0x4d)	/* Intr Ctrl reg 1 */

#define MCFSIM_ICR2		(MCF_MBAR + 0x4e)	/* Intr Ctrl reg 2 */

#define MCFSIM_ICR3		(MCF_MBAR + 0x4f)	/* Intr Ctrl reg 3 */

#define MCFSIM_ICR4		(MCF_MBAR + 0x50)	/* Intr Ctrl reg 4 */

#define MCFSIM_ICR5		(MCF_MBAR + 0x51)	/* Intr Ctrl reg 5 */

#define MCFSIM_ICR6		(MCF_MBAR + 0x52)	/* Intr Ctrl reg 6 */

#define MCFSIM_ICR7		(MCF_MBAR + 0x53)	/* Intr Ctrl reg 7 */

#define MCFSIM_ICR8		(MCF_MBAR + 0x54)	/* Intr Ctrl reg 8 */

#define MCFSIM_ICR9		(MCF_MBAR + 0x55)	/* Intr Ctrl reg 9 */

#define MCFSIM_ICR10		(MCF_MBAR + 0x56)	/* Intr Ctrl reg 10 */

#define MCFSIM_ICR11		(MCF_MBAR + 0x57)	/* Intr Ctrl reg 11 */



#define MCFSIM_CSAR0		(MCF_MBAR + 0x80)	/* CS 0 Address reg */

#define MCFSIM_CSMR0		(MCF_MBAR + 0x84)	/* CS 0 Mask reg */

#define MCFSIM_CSCR0		(MCF_MBAR + 0x8a)	/* CS 0 Control reg */

#define MCFSIM_CSAR1		(MCF_MBAR + 0x8c)	/* CS 1 Address reg */

#define MCFSIM_CSMR1		(MCF_MBAR + 0x90)	/* CS 1 Mask reg */

#define MCFSIM_CSCR1		(MCF_MBAR + 0x96)	/* CS 1 Control reg */

#define MCFSIM_CSAR2		(MCF_MBAR + 0x98)	/* CS 2 Address reg */

#define MCFSIM_CSMR2		(MCF_MBAR + 0x9c)	/* CS 2 Mask reg */

#define MCFSIM_CSCR2		(MCF_MBAR + 0xa2)	/* CS 2 Control reg */

#define MCFSIM_CSAR3		(MCF_MBAR + 0xa4)	/* CS 3 Address reg */

#define MCFSIM_CSMR3		(MCF_MBAR + 0xa8)	/* CS 3 Mask reg */

#define MCFSIM_CSCR3		(MCF_MBAR + 0xae)	/* CS 3 Control reg */

#define MCFSIM_CSAR4		(MCF_MBAR + 0xb0)	/* CS 4 Address reg */

#define MCFSIM_CSMR4		(MCF_MBAR + 0xb4)	/* CS 4 Mask reg */

#define MCFSIM_CSCR4		(MCF_MBAR + 0xba)	/* CS 4 Control reg */



#define MCFSIM_DCR		(MCF_MBAR + 0x100)	/* DRAM Control */

#define MCFSIM_DACR0		(MCF_MBAR + 0x108)	/* DRAM 0 Addr/Ctrl */