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Commit 7c4dd439 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: clk-pll: Add support for HF PLL Ops 



HF PLL ops would be required for CPU clocks, thus add support for the
same.

Change-Id: Iab524ad44a2132644f42c5dcd03e20cd83bb7e2e
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 6425aa80

drivers/clk/qcom/clk-pll.c

+62 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2021, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -342,3 +342,64 @@ const struct clk_ops clk_pll_sr2_ops = { 
	.determine_rate = clk_pll_determine_rate,

};

EXPORT_SYMBOL_GPL(clk_pll_sr2_ops);



static int

clk_pll_hf_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate)

{

	struct clk_pll *pll = to_clk_pll(hw);

	bool enabled;

	u32 mode, l_val;

	u32 enable_mask = PLL_OUTCTRL | PLL_BYPASSNL | PLL_RESET_N;



	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);

	enabled = (mode & enable_mask) == enable_mask;



	if (enabled)

		clk_pll_disable(hw);



	l_val = rate / prate;



	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, l_val);

	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, 0);

	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, 1);



	if (enabled)

		clk_pll_sr2_enable(hw);



	return 0;

}



static void clk_pll_hf_list_registers(struct seq_file *f, struct clk_hw *hw)

{

	struct clk_pll *pll = to_clk_pll(hw);

	int size, i, val;



	static struct clk_register_data data[] = {

		{"PLL_MODE", 0x0},

		{"PLL_L_VAL", 0x4},

		{"PLL_M_VAL", 0x8},

		{"PLL_N_VAL", 0xC},

		{"PLL_USER_CTL", 0x10},

		{"PLL_CONFIG_CTL", 0x14},

		{"PLL_STATUS_CTL", 0x1C},

	};



	size = ARRAY_SIZE(data);



	for (i = 0; i < size; i++) {

		regmap_read(pll->clkr.regmap, pll->mode_reg + data[i].offset,

									&val);

		clock_debug_output(f, false,

				"%20s: 0x%.8x\n", data[i].name, val);

	}

}



const struct clk_ops clk_pll_hf_ops = {

	.enable = clk_pll_sr2_enable,

	.disable = clk_pll_disable,

	.set_rate = clk_pll_hf_set_rate,

	.recalc_rate = clk_pll_recalc_rate,

	.determine_rate = clk_pll_determine_rate,

	.list_registers = clk_pll_hf_list_registers,

};

EXPORT_SYMBOL(clk_pll_hf_ops);

drivers/clk/qcom/clk-pll.h

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2013, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013, 2021, The Linux Foundation. All rights reserved.

 *

 * This software is licensed under the terms of the GNU General Public

 * License version 2, as published by the Free Software Foundation, and
@@ -63,6 +63,7 @@ struct clk_pll { 
extern const struct clk_ops clk_pll_ops;

extern const struct clk_ops clk_pll_vote_ops;

extern const struct clk_ops clk_pll_sr2_ops;

extern const struct clk_ops clk_pll_hf_ops;



#define to_clk_pll(_hw) container_of(to_clk_regmap(_hw), struct clk_pll, clkr)