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Commit 7c0fa0f2 authored by David S. Miller's avatar David S. Miller
Browse files

sparc64: Increase MAX_PHYS_ADDRESS_BITS to 53. 



Make sure, at compile time, that the kernel can properly support
whatever MAX_PHYS_ADDRESS_BITS is defined to.

On M7 chips, use a max_phys_bits value of 49.

Based upon a patch by Bob Picco.

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
Acked-by: default avatarBob Picco <bob.picco@oracle.com>
parent c06240c7

arch/sparc/include/asm/page_64.h

+4 −4
Original line number Diff line number Diff line
@@ -122,11 +122,11 @@ extern unsigned long PAGE_OFFSET; 


#endif /* !(__ASSEMBLY__) */



/* The maximum number of physical memory address bits we support, this

 * is used to size various tables used to manage kernel TLB misses and

 * also the sparsemem code.

/* The maximum number of physical memory address bits we support.  The

 * largest value we can support is whatever "KPGD_SHIFT + KPTE_BITS"

 * evaluates to.

 */

#define MAX_PHYS_ADDRESS_BITS	47

#define MAX_PHYS_ADDRESS_BITS	53



#define ILOG2_4MB		22

#define ILOG2_256MB		28

arch/sparc/include/asm/pgtable_64.h

+4 −0
Original line number Diff line number Diff line
@@ -67,6 +67,10 @@ 
#define PGDIR_MASK	(~(PGDIR_SIZE-1))

#define PGDIR_BITS	(PAGE_SHIFT - 3)



#if (MAX_PHYS_ADDRESS_BITS > PGDIR_SHIFT + PGDIR_BITS)

#error MAX_PHYS_ADDRESS_BITS exceeds what kernel page tables can support

#endif



#if (PGDIR_SHIFT + PGDIR_BITS) != 53

#error Page table parameters do not cover virtual address space properly.

#endif

arch/sparc/mm/init_64.c

+8 −1
Original line number Diff line number Diff line
@@ -1690,12 +1690,19 @@ static void __init setup_page_offset(void) 
		case SUN4V_CHIP_NIAGARA4:

		case SUN4V_CHIP_NIAGARA5:

		case SUN4V_CHIP_SPARC64X:

		default:

		case SUN4V_CHIP_SPARC_M6:

			/* T4 and later support 52-bit virtual addresses.  */

			sparc64_va_hole_top =    0xfff8000000000000UL;

			sparc64_va_hole_bottom = 0x0008000000000000UL;

			max_phys_bits = 47;

			break;

		case SUN4V_CHIP_SPARC_M7:

		default:

			/* M7 and later support 52-bit virtual addresses.  */

			sparc64_va_hole_top =    0xfff8000000000000UL;

			sparc64_va_hole_bottom = 0x0008000000000000UL;

			max_phys_bits = 49;

			break;

		}

	}