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Commit 7b7805e5 authored by Hugues Fruchet's avatar Hugues Fruchet Committed by Mauro Carvalho Chehab
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media: stm32-dcmi: revisit control register handling 



Simplify bits handling of DCMI_CR register.

Signed-off-by: default avatarHugues Fruchet <hugues.fruchet@st.com>
Signed-off-by: default avatarHans Verkuil <hansverk@cisco.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@s-opensource.com>
parent 134e15e6

drivers/media/platform/stm32/stm32-dcmi.c

+4 −10
Original line number Original line Diff line number Diff line
@@ -490,7 +490,7 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) 
{

{

	struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);

	struct stm32_dcmi *dcmi = vb2_get_drv_priv(vq);

	struct dcmi_buf *buf, *node;

	struct dcmi_buf *buf, *node;

	u32 val;

	u32 val = 0;

	int ret;

	int ret;





	ret = clk_enable(dcmi->mclk);

	ret = clk_enable(dcmi->mclk);
@@ -510,22 +510,16 @@ static int dcmi_start_streaming(struct vb2_queue *vq, unsigned int count) 




	spin_lock_irq(&dcmi->irqlock);

	spin_lock_irq(&dcmi->irqlock);





	val = reg_read(dcmi->regs, DCMI_CR);



	val &= ~(CR_PCKPOL | CR_HSPOL | CR_VSPOL |

		 CR_EDM_0 | CR_EDM_1 | CR_FCRC_0 |

		 CR_FCRC_1 | CR_JPEG | CR_ESS);



	/* Set bus width */

	/* Set bus width */

	switch (dcmi->bus.bus_width) {

	switch (dcmi->bus.bus_width) {

	case 14:

	case 14:

		val &= CR_EDM_0 + CR_EDM_1;

		val |= CR_EDM_0 | CR_EDM_1;

		break;

		break;

	case 12:

	case 12:

		val &= CR_EDM_1;

		val |= CR_EDM_1;

		break;

		break;

	case 10:

	case 10:

		val &= CR_EDM_0;

		val |= CR_EDM_0;

		break;

		break;

	default:

	default:

		/* Set bus width to 8 bits by default */

		/* Set bus width to 8 bits by default */