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Commit 7b3cc2b1 authored by Dan Williams's avatar Dan Williams
Browse files

async_tx: build-time toggling of async_{syndrome,xor}_val dma support 



ioat3.2 does not support asynchronous error notifications which makes
the driver experience latencies when non-zero pq validate results are
expected.  Provide a mechanism for turning off async_xor_val and
async_syndrome_val via Kconfig.  This approach is generally useful for
any driver that specifies ASYNC_TX_DISABLE_CHANNEL_SWITCH and would like
to force the async_tx api to fall back to the synchronous path for
certain operations.

Signed-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 4499a24d

crypto/async_tx/Kconfig

+5 −0
Original line number Original line Diff line number Diff line
@@ -23,3 +23,8 @@ config ASYNC_RAID6_RECOV 
	select ASYNC_CORE

	select ASYNC_CORE

	select ASYNC_PQ

	select ASYNC_PQ





config ASYNC_TX_DISABLE_PQ_VAL_DMA

	bool



config ASYNC_TX_DISABLE_XOR_VAL_DMA

	bool

crypto/async_tx/async_pq.c

+11 −3
Original line number Original line Diff line number Diff line
@@ -240,6 +240,16 @@ async_gen_syndrome(struct page **blocks, unsigned int offset, int disks, 
}

}

EXPORT_SYMBOL_GPL(async_gen_syndrome);

EXPORT_SYMBOL_GPL(async_gen_syndrome);





static inline struct dma_chan *

pq_val_chan(struct async_submit_ctl *submit, struct page **blocks, int disks, size_t len)

{

	#ifdef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA

	return NULL;

	#endif

	return async_tx_find_channel(submit, DMA_PQ_VAL, NULL, 0,  blocks,

				     disks, len);

}



/**

/**

 * async_syndrome_val - asynchronously validate a raid6 syndrome

 * async_syndrome_val - asynchronously validate a raid6 syndrome

 * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1

 * @blocks: source blocks from idx 0..disks-3, P @ disks-2 and Q @ disks-1
@@ -260,9 +270,7 @@ async_syndrome_val(struct page **blocks, unsigned int offset, int disks, 
		   size_t len, enum sum_check_flags *pqres, struct page *spare,

		   size_t len, enum sum_check_flags *pqres, struct page *spare,

		   struct async_submit_ctl *submit)

		   struct async_submit_ctl *submit)

{

{

	struct dma_chan *chan = async_tx_find_channel(submit, DMA_PQ_VAL,

	struct dma_chan *chan = pq_val_chan(submit, blocks, disks, len);

						      NULL, 0,  blocks, disks,

						      len);

	struct dma_device *device = chan ? chan->device : NULL;

	struct dma_device *device = chan ? chan->device : NULL;

	struct dma_async_tx_descriptor *tx;

	struct dma_async_tx_descriptor *tx;

	unsigned char coefs[disks-2];

	unsigned char coefs[disks-2];

crypto/async_tx/async_xor.c

+12 −3
Original line number Original line Diff line number Diff line
@@ -234,6 +234,17 @@ static int page_is_zero(struct page *p, unsigned int offset, size_t len) 
		memcmp(a, a + 4, len - 4) == 0);

		memcmp(a, a + 4, len - 4) == 0);

}

}





static inline struct dma_chan *

xor_val_chan(struct async_submit_ctl *submit, struct page *dest,

		 struct page **src_list, int src_cnt, size_t len)

{

	#ifdef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA

	return NULL;

	#endif

	return async_tx_find_channel(submit, DMA_XOR_VAL, &dest, 1, src_list,

				     src_cnt, len);

}



/**

/**

 * async_xor_val - attempt a xor parity check with a dma engine.

 * async_xor_val - attempt a xor parity check with a dma engine.

 * @dest: destination page used if the xor is performed synchronously

 * @dest: destination page used if the xor is performed synchronously
@@ -255,9 +266,7 @@ async_xor_val(struct page *dest, struct page **src_list, unsigned int offset, 
	      int src_cnt, size_t len, enum sum_check_flags *result,

	      int src_cnt, size_t len, enum sum_check_flags *result,

	      struct async_submit_ctl *submit)

	      struct async_submit_ctl *submit)

{

{

	struct dma_chan *chan = async_tx_find_channel(submit, DMA_XOR_VAL,

	struct dma_chan *chan = xor_val_chan(submit, dest, src_list, src_cnt, len);

						      &dest, 1, src_list,

						      src_cnt, len);

	struct dma_device *device = chan ? chan->device : NULL;

	struct dma_device *device = chan ? chan->device : NULL;

	struct dma_async_tx_descriptor *tx = NULL;

	struct dma_async_tx_descriptor *tx = NULL;

	dma_addr_t *dma_src = NULL;

	dma_addr_t *dma_src = NULL;

drivers/dma/Kconfig

+2 −0
Original line number Original line Diff line number Diff line
@@ -26,6 +26,8 @@ config INTEL_IOATDMA 
	select DMA_ENGINE

	select DMA_ENGINE

	select DCA

	select DCA

	select ASYNC_TX_DISABLE_CHANNEL_SWITCH

	select ASYNC_TX_DISABLE_CHANNEL_SWITCH

	select ASYNC_TX_DISABLE_PQ_VAL_DMA

	select ASYNC_TX_DISABLE_XOR_VAL_DMA

	help

	help

	  Enable support for the Intel(R) I/OAT DMA engine present

	  Enable support for the Intel(R) I/OAT DMA engine present

	  in recent Intel Xeon chipsets.

	  in recent Intel Xeon chipsets.

drivers/dma/dmaengine.c

+6 −0
Original line number Original line Diff line number Diff line
@@ -632,16 +632,22 @@ static bool device_has_all_tx_types(struct dma_device *device) 
	#if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)

	#if defined(CONFIG_ASYNC_XOR) || defined(CONFIG_ASYNC_XOR_MODULE)

	if (!dma_has_cap(DMA_XOR, device->cap_mask))

	if (!dma_has_cap(DMA_XOR, device->cap_mask))

		return false;

		return false;



	#ifndef CONFIG_ASYNC_TX_DISABLE_XOR_VAL_DMA

	if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))

	if (!dma_has_cap(DMA_XOR_VAL, device->cap_mask))

		return false;

		return false;

	#endif

	#endif

	#endif





	#if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)

	#if defined(CONFIG_ASYNC_PQ) || defined(CONFIG_ASYNC_PQ_MODULE)

	if (!dma_has_cap(DMA_PQ, device->cap_mask))

	if (!dma_has_cap(DMA_PQ, device->cap_mask))

		return false;

		return false;



	#ifndef CONFIG_ASYNC_TX_DISABLE_PQ_VAL_DMA

	if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))

	if (!dma_has_cap(DMA_PQ_VAL, device->cap_mask))

		return false;

		return false;

	#endif

	#endif

	#endif





	return true;

	return true;

}

}