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Commit 7b39e985 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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ARM: dts: r8a7792: Correct Z clock



Unlike other R-Car Gen2 SoCs with Cortex-A15 CPU cores, R-Car V2H does
not have a programmable Z clock (Cortex-A15 CPU core clock), but uses a
fixed divider.
This is similar to the Z2 clock (Cortex-A7 CPU core clock) on R-Car E2.

Hence:
  - Remove the Z clock output from the cpg_clocks node, as this implied
    a programmable clock,
  - Add the Z clock as a fixed factor clock,
  - Let the first CPU node point to the new Z clock,
  - Remove the Z clock index from the bindings (this definition was used
    by r8a7792.dtsi only, and was not a contract between DT and driver).

Fixes: 7c4163aa ("ARM: dts: r8a7792: initial SoC device tree")
Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 1cd90280
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+9 −2
Original line number Diff line number Diff line
@@ -46,7 +46,7 @@
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1000000000>;
			clocks = <&cpg_clocks R8A7792_CLK_Z>;
			clocks = <&z_clk>;
			power-domains = <&sysc R8A7792_PD_CA15_CPU0>;
			next-level-cache = <&L2_CA15>;
		};
@@ -766,7 +766,7 @@
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll3",
					     "lb", "qspi", "z";
					     "lb", "qspi";
			#power-domain-cells = <0>;
		};

@@ -778,6 +778,13 @@
			clock-div = <2>;
			clock-mult = <1>;
		};
		z_clk: z {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7792_CLK_PLL0>;
			#clock-cells = <0>;
			clock-div = <1>;
			clock-mult = <1>;
		};
		zx_clk: zx {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7792_CLK_PLL1>;
+0 −1
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@
#define R8A7792_CLK_PLL3		3
#define R8A7792_CLK_LB			4
#define R8A7792_CLK_QSPI		5
#define R8A7792_CLK_Z			6

/* MSTP0 */
#define R8A7792_CLK_MSIOF0		0