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Commit 7b337e61 authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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arm64: dts: r8a7795: Add L2 cache-controller nodes 



Add device nodes for the L2 caches, and link the CPU node to its L2
cache node.

The L2 cache for the Cortex-A57 CPU cores is 2 MiB large (organized as
128 KiB x 16 ways).

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarDirk Behme <dirk.behme@gmail.com>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent a3fc85e2

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+8 −0
Original line number Diff line number Diff line
@@ -39,6 +39,7 @@ 
			compatible = "arm,cortex-a57", "arm,armv8";

			reg = <0x0>;

			device_type = "cpu";

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

		};
@@ -46,22 +47,29 @@ 
			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x1>;

			device_type = "cpu";

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

		};

		a57_2: cpu@2 {

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x2>;

			device_type = "cpu";

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

		};

		a57_3: cpu@3 {

			compatible = "arm,cortex-a57","arm,armv8";

			reg = <0x3>;

			device_type = "cpu";

			next-level-cache = <&L2_CA57>;

			enable-method = "psci";

		};

	};



	L2_CA57: cache-controller@0 {

		compatible = "cache";

	};



	extal_clk: extal {

		compatible = "fixed-clock";

		#clock-cells = <0>;