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Commit 7ae0ae4a authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'spi-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi 

Pull spi updates from Mark Brown:
 "Quite a lot of cleanup and maintainence work going on this release in
  various drivers, and also a fix for a nasty locking issue in the core:

   - A fix for locking issues when external drivers explicitly locked
     the bus with spi_bus_lock() - we were using the same lock to both
     control access to the physical bus in multi-threaded I/O operations
     and exclude multiple callers.

     Confusion between these two caused us to have scenarios where we
     were dropping locks.  These are fixed by splitting into two
     separate locks like should have been done originally, making
     everything much clearer and correct.

   - Support for DMA in spi_flash_read().

   - Support for instantiating spidev on ACPI systems, including some
     test devices used in Windows validation.

   - Use of the core DMA mapping functionality in the McSPI driver.

   - Start of support for ThunderX SPI controllers, involving a very big
     set of changes to the Cavium driver.

   - Support for Braswell, Exynos 5433, Kaby Lake, Merrifield, RK3036,
     RK3228, RK3368 controllers"

* tag 'spi-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: (64 commits)
  spi: Split bus and I/O locking
  spi: octeon: Split driver into Octeon specific and common parts
  spi: octeon: Move include file from arch/mips to drivers/spi
  spi: octeon: Put register offsets into a struct
  spi: octeon: Store system clock freqency in struct octeon_spi
  spi: octeon: Convert driver to use readq()/writeq() functions
  spi: pic32-sqi: fixup wait_for_completion_timeout return handling
  spi: pic32: fixup wait_for_completion_timeout return handling
  spi: rockchip: limit transfers to (64K - 1) bytes
  spi: xilinx: Return IRQ_NONE if no interrupts were detected
  spi: xilinx: Handle errors from platform_get_irq()
  spi: s3c64xx: restore removed comments
  spi: s3c64xx: add Exynos5433 compatible for ioclk handling
  spi: s3c64xx: use error code from clk_prepare_enable()
  spi: s3c64xx: rename goto labels to meaningful names
  spi: s3c64xx: document the clocks and the clock-name property
  spi: s3c64xx: add exynos5433 spi compatible
  spi: s3c64xx: fix reference leak to master in s3c64xx_spi_remove()
  spi: spi-sh: Remove deprecated create_singlethread_workqueue
  spi: spi-topcliff-pch: Remove deprecated create_singlethread_workqueue
  ...
parents 607e11ab dec34e8b

Documentation/devicetree/bindings/spi/fsl-imx-cspi.txt

+3 −2
Original line number Diff line number Diff line
@@ -11,7 +11,6 @@ Required properties: 
  - "fsl,imx51-ecspi" for SPI compatible with the one integrated on i.MX51

- reg : Offset and length of the register set for the device

- interrupts : Should contain CSPI/eCSPI interrupt

- fsl,spi-num-chipselects : Contains the number of the chipselect

- cs-gpios : Specifies the gpio pins to be used for chipselects.

- clocks : Clock specifiers for both ipg and per clocks.

- clock-names : Clock names should include both "ipg" and "per"
@@ -21,6 +20,9 @@ See the clock consumer binding, 
		Documentation/devicetree/bindings/dma/dma.txt

- dma-names: DMA request names should include "tx" and "rx" if present.



Obsolete properties:

- fsl,spi-num-chipselects : Contains the number of the chipselect



Example:



ecspi@70010000 {
@@ -29,7 +31,6 @@ ecspi@70010000 { 
	compatible = "fsl,imx51-ecspi";

	reg = <0x70010000 0x4000>;

	interrupts = <36>;

	fsl,spi-num-chipselects = <2>;

	cs-gpios = <&gpio3 24 0>, /* GPIO3_24 */

		   <&gpio3 25 0>; /* GPIO3_25 */

	dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;

Documentation/devicetree/bindings/spi/spi-bus.txt

+18 −17
Original line number Diff line number Diff line
@@ -12,7 +12,6 @@ The SPI master node requires the following properties: 
- #size-cells     - should be zero.

- compatible      - name of SPI bus controller following generic names

		recommended practice.

- cs-gpios	  - (optional) gpios chip select.

No other properties are required in the SPI bus node.  It is assumed

that a driver for an SPI bus device will understand that it is an SPI bus.

However, the binding does not attempt to define the specific method for
@@ -22,11 +21,12 @@ assumption that board specific platform code will be used to manage 
chip selects.  Individual drivers can define additional properties to

support describing the chip select layout.



Optional property:

- num-cs : total number of chipselects

Optional properties:

- cs-gpios	  - gpios chip select.

- num-cs	  - total number of chipselects.



If cs-gpios is used the number of chip select will automatically increased

with max(cs-gpios > hw cs)

If cs-gpios is used the number of chip selects will be increased automatically

with max(cs-gpios > hw cs).



So if for example the controller has 2 CS lines, and the cs-gpios

property looks like this:
@@ -45,27 +45,28 @@ SPI slave nodes must be children of the SPI master node and can 
contain the following properties.

- reg             - (required) chip select address of device.

- compatible      - (required) name of SPI device following generic names

    		recommended practice

- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz

		recommended practice.

- spi-max-frequency - (required) Maximum SPI clocking speed of device in Hz.

- spi-cpol        - (optional) Empty property indicating device requires

    		inverse clock polarity (CPOL) mode

		inverse clock polarity (CPOL) mode.

- spi-cpha        - (optional) Empty property indicating device requires

    		shifted clock phase (CPHA) mode

		shifted clock phase (CPHA) mode.

- spi-cs-high     - (optional) Empty property indicating device requires

    		chip select active high

		chip select active high.

- spi-3wire       - (optional) Empty property indicating device requires

		3-wire mode.

- spi-lsb-first   - (optional) Empty property indicating device requires

		LSB first mode.

- spi-tx-bus-width - (optional) The bus width(number of data wires) that

- spi-tx-bus-width - (optional) The bus width (number of data wires) that is

                      used for MOSI. Defaults to 1 if not present.

- spi-rx-bus-width - (optional) The bus width(number of data wires) that

- spi-rx-bus-width - (optional) The bus width (number of data wires) that is

                      used for MISO. Defaults to 1 if not present.

- spi-rx-delay-us  - (optional) Microsecond delay after a read transfer.

- spi-tx-delay-us  - (optional) Microsecond delay after a write transfer.



Some SPI controllers and devices support Dual and Quad SPI transfer mode.

It allows data in the SPI system to be transferred in 2 wires(DUAL) or 4 wires(QUAD).

It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4

wires (QUAD).

Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is

only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).

Dual/Quad mode is not allowed when 3-wire mode is used.

Documentation/devicetree/bindings/spi/spi-clps711x.txt

0 → 100644
+33 −0
Original line number Diff line number Diff line 
Serial Peripheral Interface on Cirrus Logic CL-PS71xx, EP72xx, EP73xx



Required properties

- #address-cells: must be <1>

- #size-cells: must be <0>

- compatible: should include "cirrus,ep7209-spi"

- reg: Address and length of one register range

- interrupts: one interrupt line

- clocks: One entry, refers to the SPI bus clock

- cs-gpios: Specifies the gpio pins to be used for chipselects.

	    See: Documentation/devicetree/bindings/spi/spi-bus.txt



An additional register is present in the system controller,

which is assumed to be in the same device tree, with and marked

as compatible with "cirrus,ep7209-syscon3".



Example:



spi@80000500 {

	#address-cells = <1>;

	#size-cells = <0>;

	compatible = "cirrus,ep7209-spi";

	reg = <0x80000500 0x4>;

	interrupts = <15>;

	clocks = <&clks CLPS711X_CLK_SPI>;

	status = "disabled";

};



syscon3: syscon@80002200 {

	compatible = "cirrus,ep7209-syscon3", "syscon";

	reg = <0x80002200 0x40>;

};

Documentation/devicetree/bindings/spi/spi-davinci.txt

+1 −1
Original line number Diff line number Diff line
@@ -21,7 +21,7 @@ Required properties: 
	IP to the interrupt controller within the SoC. Possible values

	are 0 and 1. Manual says one of the two possible interrupt

	lines can be tied to the interrupt controller. Set this

	based on a specifc SoC configuration.

	based on a specific SoC configuration.

- interrupts: interrupt number mapped to CPU.

- clocks: spi clk phandle

Documentation/devicetree/bindings/spi/spi-orion.txt

+48 −1
Original line number Diff line number Diff line
@@ -8,7 +8,15 @@ Required properties: 
    - "marvell,armada-380-spi", for the Armada 38x SoCs

    - "marvell,armada-390-spi", for the Armada 39x SoCs

    - "marvell,armada-xp-spi", for the Armada XP SoCs

- reg : offset and length of the register set for the device

- reg : offset and length of the register set for the device.

	This property can optionally have additional entries to configure

	the SPI direct access mode that some of the Marvell SoCs support

	additionally to the normal indirect access (PIO) mode. The values

	for the MBus "target" and "attribute" are defined in the Marvell

	SoC "Functional Specifications" Manual in the chapter "Marvell

	Core Processor Address Decoding".

	The eight register sets following the control registers refer to

	chip-select lines 0 through 7 respectively.

- cell-index : Which of multiple SPI controllers is this.

Optional properties:

- interrupts : Is currently not used.
@@ -23,3 +31,42 @@ Example: 
	       interrupts = <23>;

	       status = "disabled";

       };



Example with SPI direct mode support (optionally):

	spi0: spi@10600 {

		compatible = "marvell,orion-spi";

		#address-cells = <1>;

		#size-cells = <0>;

		cell-index = <0>;

		reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x28>, /* control */

		      <MBUS_ID(0x01, 0x1e) 0 0xffffffff>, /* CS0 */

		      <MBUS_ID(0x01, 0x5e) 0 0xffffffff>, /* CS1 */

		      <MBUS_ID(0x01, 0x9e) 0 0xffffffff>, /* CS2 */

		      <MBUS_ID(0x01, 0xde) 0 0xffffffff>, /* CS3 */

		      <MBUS_ID(0x01, 0x1f) 0 0xffffffff>, /* CS4 */

		      <MBUS_ID(0x01, 0x5f) 0 0xffffffff>, /* CS5 */

		      <MBUS_ID(0x01, 0x9f) 0 0xffffffff>, /* CS6 */

		      <MBUS_ID(0x01, 0xdf) 0 0xffffffff>; /* CS7 */

		interrupts = <23>;

		status = "disabled";

	};



To enable the direct mode, the board specific 'ranges' property in the

'soc' node needs to add the entries for the desired SPI controllers

and its chip-selects that are used in the direct mode instead of PIO

mode. Here an example for this (SPI controller 0, device 1 and SPI

controller 1, device 2 are used in direct mode. All other SPI device

are used in the default indirect (PIO) mode):

	soc {

		/*

		 * Enable the SPI direct access by configuring an entry

		 * here in the board-specific ranges property

		 */

		ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000>,	/* internal regs */

			 <MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>,	/* BootROM       */

			 <MBUS_ID(0x01, 0x5e) 0 0 0xf1100000 0x10000>,	/* SPI0-DEV1 */

			 <MBUS_ID(0x01, 0x9a) 0 0 0xf1110000 0x10000>;	/* SPI1-DEV2 */



For further information on the MBus bindings, please see the MBus

DT documentation:

Documentation/devicetree/bindings/bus/mvebu-mbus.txt