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Commit 7abc003b authored by Sayali Lokhande's avatar Sayali Lokhande
Browse files

ARM: dts: msm: Add UFS support for lagoon 

This change adds UFS support for lagoon rumi platform.

Change-Id: I15af0e012dc5243606d0e86e71c686ca15e7837f
parent f98f34d4

qcom/lagoon-pinctrl.dtsi

+46 −0
Original line number Diff line number Diff line
@@ -7,5 +7,51 @@ 
		#gpio-cells = <2>;

		interrupt-controller;

		#interrupt-cells = <2>;



		ufs_dev_reset_assert: ufs_dev_reset_assert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * UFS_RESET driver strengths are having

				 * different values/steps compared to typical

				 * GPIO drive strengths.

				 *

				 * Following table clarifies:

				 *

				 * HDRV value | UFS_RESET | Typical GPIO

				 *   (dec)    |   (mA)    |    (mA)

				 *     0      |   0.8     |    2

				 *     1      |   1.55    |    4

				 *     2      |   2.35    |    6

				 *     3      |   3.1     |    8

				 *     4      |   3.9     |    10

				 *     5      |   4.65    |    12

				 *     6      |   5.4     |    14

				 *     7      |   6.15    |    16

				 *

				 * POR value for UFS_RESET HDRV is 3 which means

				 * 3.1mA and we want to use that. Hence just

				 * specify 8mA to "drive-strength" binding and

				 * that should result into writing 3 to HDRV

				 * field.

				 */

				drive-strength = <8>;	/* default: 3.1 mA */

				output-low; /* active low reset */

			};

		};



		ufs_dev_reset_deassert: ufs_dev_reset_deassert {

			config {

				pins = "ufs_reset";

				bias-pull-down;		/* default: pull down */

				/*

				 * default: 3.1 mA

				 * check comments under ufs_dev_reset_assert

				 */

				drive-strength = <8>;

				output-high; /* active low reset */

			};

		};

	};

};

qcom/lagoon-rumi.dtsi

+30 −0
Original line number Diff line number Diff line
@@ -8,6 +8,36 @@ 
	};

};



&ufsphy_mem {

	compatible = "qcom,ufs-phy-qrbtc-sdm845";



	vdda-phy-supply = <&L18A>;

	vdda-pll-supply = <&L22A>;

	vdda-phy-max-microamp = <62900>;

	vdda-pll-max-microamp = <18300>;



	status = "ok";

};



&ufshc_mem {

	limit-tx-hs-gear = <1>;

	limit-rx-hs-gear = <1>;

	scsi-cmd-timeout = <300000>;



	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;

	vdd-hba-fixed-regulator;

	vcc-supply = <&L7E>;

	vccq2-supply = <&L12A>;

	vcc-max-microamp = <800000>;

	vccq2-max-microamp = <800000>;



	qcom,vddp-ref-clk-supply = <&L22A>;

	qcom,vddp-ref-clk-max-microamp = <100>;



	qcom,disable-lpm;

	status = "ok";

};



&wdog {

	status = "disabled";

};

qcom/lagoon.dtsi

+131 −0
Original line number Diff line number Diff line
@@ -10,6 +10,10 @@ 
	#size-cells = <2>;

	memory { device_type = "memory"; reg = <0 0 0 0>; };



	aliases {

		ufshc1 = &ufshc_mem; /* Embedded UFS slot */

	};



	cpus {

		#address-cells = <2>;

		#size-cells = <0>;
@@ -341,6 +345,133 @@ 
		interrupt-parent = <&intc>;

	};



	ufsphy_mem: ufsphy_mem@1d87000 {

		reg = <0x1d87000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;



		lanes-per-direction = <2>;



		clock-names = "ref_clk_src",

			"ref_clk",

			"ref_aux_clk";

		clocks = <&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_MEM_CLKREF_CLK>,

			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;



		status = "disabled";

	};



	ufshc_mem: ufshc@1d84000 {

		compatible = "qcom,ufshc";

		reg = <0x1d84000 0x3000>;

		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufsphy_mem>;

		phy-names = "ufsphy";



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */

		spm-level = <5>;



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&gcc GCC_UFS_PHY_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,

			<&gcc GCC_UFS_PHY_AHB_CLK>,

			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,

			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			<&rpmhcc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<50000000 200000000>,

			<0 0>,

			<0 0>,

			<37500000 150000000>,

			<75000000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <22>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<123 512 0 0>, <1 757 0 0>,          /* No vote */

		<123 512 922 0>, <1 757 1000 0>,     /* PWM G1 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G3 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G4 */

		<123 512 1844 0>, <1 757 1000 0>,    /* PWM G1 L2 */

		<123 512 3688 0>, <1 757 1000 0>,    /* PWM G2 L2 */

		<123 512 7376 0>, <1 757 1000 0>,    /* PWM G3 L2 */

		<123 512 14752 0>, <1 757 1000 0>,   /* PWM G4 L2 */

		<123 512 127796 0>, <1 757 1000 0>,  /* HS G1 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G2 RA */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RA */

		<123 512 255591 0>, <1 757 1000 0>,  /* HS G1 RA L2 */

		<123 512 511181 0>, <1 757 1000 0>,  /* HS G2 RA L2 */

		<123 512 4194304 0>, <1 757 204800 0>, /* HS G3 RA L2 */

		<123 512 149422 0>, <1 757 1000 0>,  /* HS G1 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G2 RB */

		<123 512 2097152 0>, <1 757 102400 0>,  /* HS G3 RB */

		<123 512 298189 0>, <1 757 1000 0>,  /* HS G1 RB L2 */

		<123 512 596378 0>, <1 757 1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<123 512 4194304 0>, <1 757 204800 409600>, /* HS G3 RB L2 */

		<123 512 7643136 0>, <1 757 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x3f 0xc0>;

		qcom,pm-qos-cpu-group-latency-us = <67 67>;

		qcom,pm-qos-default-cpu = <0>;



		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";

		pinctrl-0 = <&ufs_dev_reset_assert>;

		pinctrl-1 = <&ufs_dev_reset_deassert>;



		resets = <&gcc GCC_UFS_PHY_BCR>;

		reset-names = "core_reset";

		non-removable;



		status = "disabled";

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,