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Commit 7a9cc1ad authored by Greg Ungerer's avatar Greg Ungerer Committed by Shawn Guo
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ARM: imx: add clocking support code for the IMX50 SoC 



Add code to support the specific clock tree of the Freescale IMX50 SoC.
It can use much of the common IMX51/IMX53 clocking code.

Signed-off-by: default avatarGreg Ungerer <gerg@uclinux.org>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent ad364a70

arch/arm/mach-imx/clk-imx51-imx53.c

+58 −0
Original line number Diff line number Diff line
@@ -365,6 +365,64 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, 
	clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */

}



static void __init mx50_clocks_init(struct device_node *np)

{

	void __iomem *base;

	unsigned long r;

	int i, irq;



	clk[pll1_sw] = imx_clk_pllv2("pll1_sw", "osc", MX53_DPLL1_BASE);

	clk[pll2_sw] = imx_clk_pllv2("pll2_sw", "osc", MX53_DPLL2_BASE);

	clk[pll3_sw] = imx_clk_pllv2("pll3_sw", "osc", MX53_DPLL3_BASE);



	clk[esdhc1_per_gate] = imx_clk_gate2("esdhc1_per_gate", "esdhc_a_podf", MXC_CCM_CCGR3, 2);

	clk[esdhc2_per_gate] = imx_clk_gate2("esdhc2_per_gate", "esdhc_c_sel", MXC_CCM_CCGR3, 6);

	clk[esdhc3_per_gate] = imx_clk_gate2("esdhc3_per_gate", "esdhc_b_podf", MXC_CCM_CCGR3, 10);

	clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);

	clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);

	clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);

	clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);



	clk[cko1_sel] = imx_clk_mux("cko1_sel", MXC_CCM_CCOSR, 0, 4,

				mx53_cko1_sel, ARRAY_SIZE(mx53_cko1_sel));

	clk[cko1_podf] = imx_clk_divider("cko1_podf", "cko1_sel", MXC_CCM_CCOSR, 4, 3);

	clk[cko1] = imx_clk_gate2("cko1", "cko1_podf", MXC_CCM_CCOSR, 7);



	clk[cko2_sel] = imx_clk_mux("cko2_sel", MXC_CCM_CCOSR, 16, 5,

				mx53_cko2_sel, ARRAY_SIZE(mx53_cko2_sel));

	clk[cko2_podf] = imx_clk_divider("cko2_podf", "cko2_sel", MXC_CCM_CCOSR, 21, 3);

	clk[cko2] = imx_clk_gate2("cko2", "cko2_podf", MXC_CCM_CCOSR, 24);



	for (i = 0; i < ARRAY_SIZE(clk); i++)

		if (IS_ERR(clk[i]))

			pr_err("i.MX50 clk %d: register failed with %ld\n",

				i, PTR_ERR(clk[i]));



	clk_data.clks = clk;

	clk_data.clk_num = ARRAY_SIZE(clk);

	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);



	mx5_clocks_common_init(0, 0, 0, 0);



	/* set SDHC root clock to 200MHZ*/

	clk_set_rate(clk[esdhc_a_podf], 200000000);

	clk_set_rate(clk[esdhc_b_podf], 200000000);



	clk_prepare_enable(clk[iim_gate]);

	imx_print_silicon_rev("i.MX50", IMX_CHIP_REVISION_1_1);

	clk_disable_unprepare(clk[iim_gate]);



	r = clk_round_rate(clk[usboh3_per_gate], 54000000);

	clk_set_rate(clk[usboh3_per_gate], r);



	np = of_find_compatible_node(NULL, NULL, "fsl,imx50-gpt");

	base = of_iomap(np, 0);

	WARN_ON(!base);

	irq = irq_of_parse_and_map(np, 0);

	mxc_timer_init(base, irq);

}

CLK_OF_DECLARE(imx50_ccm, "fsl,imx50-ccm", mx50_clocks_init);



int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,

			unsigned long rate_ckih1, unsigned long rate_ckih2)

{