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Commit 7a753c3f authored by Samuel Li's avatar Samuel Li Committed by Alex Deucher
Browse files

drm/amdgpu: Update SMC/DPM for Stoney 



Stoney is SMC 8.x.

Signed-off-by: default avatarSamuel Li <samuel.li@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aade2f04

drivers/gpu/drm/amd/amdgpu/cz_dpm.c

+17 −4
Original line number Diff line number Diff line
@@ -1262,6 +1262,7 @@ static void cz_apply_state_adjust_rules(struct amdgpu_device *adev, 


static int cz_dpm_enable(struct amdgpu_device *adev)

{

	const char *chip_name;

	int ret = 0;



	/* renable will hang up SMU, so check first */
@@ -1270,21 +1271,33 @@ static int cz_dpm_enable(struct amdgpu_device *adev) 


	cz_program_voting_clients(adev);



	switch (adev->asic_type) {

	case CHIP_CARRIZO:

		chip_name = "carrizo";

		break;

	case CHIP_STONEY:

		chip_name = "stoney";

		break;

	default:

		BUG();

	}





	ret = cz_start_dpm(adev);

	if (ret) {

		DRM_ERROR("Carrizo DPM enable failed\n");

		DRM_ERROR("%s DPM enable failed\n", chip_name);

		return -EINVAL;

	}



	ret = cz_program_bootup_state(adev);

	if (ret) {

		DRM_ERROR("Carrizo bootup state program failed\n");

		DRM_ERROR("%s bootup state program failed\n", chip_name);

		return -EINVAL;

	}



	ret = cz_enable_didt(adev, true);

	if (ret) {

		DRM_ERROR("Carrizo enable di/dt failed\n");

		DRM_ERROR("%s enable di/dt failed\n", chip_name);

		return -EINVAL;

	}
@@ -1351,7 +1364,7 @@ static int cz_dpm_disable(struct amdgpu_device *adev) 


	ret = cz_enable_didt(adev, false);

	if (ret) {

		DRM_ERROR("Carrizo disable di/dt failed\n");

		DRM_ERROR("disable di/dt failed\n");

		return -EINVAL;

	}

drivers/gpu/drm/amd/amdgpu/cz_smc.c

+48 −12
Original line number Diff line number Diff line
@@ -312,13 +312,16 @@ int cz_smu_start(struct amdgpu_device *adev) 
				UCODE_ID_CP_MEC_JT1_MASK |

				UCODE_ID_CP_MEC_JT2_MASK;



	if (adev->asic_type == CHIP_STONEY)

		fw_to_check &= ~(UCODE_ID_SDMA1_MASK | UCODE_ID_CP_MEC_JT2_MASK);



	cz_smu_request_load_fw(adev);

	ret = cz_smu_check_fw_load_finish(adev, fw_to_check);

	if (ret)

		return ret;



	/* manually load MEC firmware for CZ */

	if (adev->asic_type == CHIP_CARRIZO) {

	if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {

		ret = cz_load_mec_firmware(adev);

		if (ret) {

			dev_err(adev->dev, "(%d) Mec Firmware load failed\n", ret);
@@ -336,6 +339,9 @@ int cz_smu_start(struct amdgpu_device *adev) 
				AMDGPU_CPMEC2_UCODE_LOADED |

				AMDGPU_CPRLC_UCODE_LOADED;



	if (adev->asic_type == CHIP_STONEY)

		adev->smu.fw_flags &= ~(AMDGPU_SDMA1_UCODE_LOADED | AMDGPU_CPMEC2_UCODE_LOADED);



	return ret;

}
@@ -601,8 +607,13 @@ static int cz_smu_construct_toc_for_vddgfx_exit(struct amdgpu_device *adev) 
				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);

		if (adev->asic_type == CHIP_STONEY) {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);

		} else {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);

		}

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, false);

	}
@@ -642,8 +653,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) 
	if (adev->firmware.smu_load) {

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);

		if (adev->asic_type == CHIP_STONEY) {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0, false);

		} else {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1, false);

		}

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE, false);

		cz_smu_populate_single_ucode_load_task(adev,
@@ -652,8 +668,13 @@ static int cz_smu_construct_toc_for_bootup(struct amdgpu_device *adev) 
				CZ_SCRATCH_ENTRY_UCODE_ID_CP_ME, false);

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);

		if (adev->asic_type == CHIP_STONEY) {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1, false);

		} else {

			cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2, false);

		}

		cz_smu_populate_single_ucode_load_task(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G, true);

	}
@@ -888,10 +909,18 @@ int cz_smu_init(struct amdgpu_device *adev) 
				CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,

				&priv->driver_buffer[priv->driver_buffer_length++]))

			goto smu_init_failed;



		if (adev->asic_type == CHIP_STONEY) {

			if (cz_smu_populate_single_firmware_entry(adev,

					CZ_SCRATCH_ENTRY_UCODE_ID_SDMA0,

					&priv->driver_buffer[priv->driver_buffer_length++]))

				goto smu_init_failed;

		} else {

			if (cz_smu_populate_single_firmware_entry(adev,

					CZ_SCRATCH_ENTRY_UCODE_ID_SDMA1,

					&priv->driver_buffer[priv->driver_buffer_length++]))

				goto smu_init_failed;

		}

		if (cz_smu_populate_single_firmware_entry(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_CP_CE,

				&priv->driver_buffer[priv->driver_buffer_length++]))
@@ -908,10 +937,17 @@ int cz_smu_init(struct amdgpu_device *adev) 
				CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,

				&priv->driver_buffer[priv->driver_buffer_length++]))

			goto smu_init_failed;

		if (adev->asic_type == CHIP_STONEY) {

			if (cz_smu_populate_single_firmware_entry(adev,

					CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT1,

					&priv->driver_buffer[priv->driver_buffer_length++]))

				goto smu_init_failed;

		} else {

			if (cz_smu_populate_single_firmware_entry(adev,

					CZ_SCRATCH_ENTRY_UCODE_ID_CP_MEC_JT2,

					&priv->driver_buffer[priv->driver_buffer_length++]))

				goto smu_init_failed;

		}

		if (cz_smu_populate_single_firmware_entry(adev,

				CZ_SCRATCH_ENTRY_UCODE_ID_RLC_G,

				&priv->driver_buffer[priv->driver_buffer_length++]))