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Commit 7a3252f8 authored by Olof Johansson's avatar Olof Johansson
Browse files

Merge branch 'for-3.5/tegra30-audio' of... 

Merge branch 'for-3.5/tegra30-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/drivers

By Stephen Warren (5) and Peter De Schrijver (1)
via Stephen Warren
* 'for-3.5/tegra30-audio' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra

:
  ARM: dt: tegra cardhu: basic audio support
  ARM: dt: tegra30.dtsi: Add audio-related nodes
  ARM: tegra: add AUXDATA required for audio
  ARM: tegra: set up audio clocks for tegra30 dt
  ARM: tegra: Initialize pll_p_out1
  ARM: tegra: provide clock aliases for AHUB configlink

Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents bd69e273 8c6a3852

arch/arm/boot/dts/tegra-cardhu.dts

+63 −0
Original line number Diff line number Diff line
@@ -51,6 +51,15 @@ 
				nvidia,pull = <2>;

				nvidia,tristate = <0>;

			};

			dap2_fs_pa2 {

				nvidia,pins =	"dap2_fs_pa2",

						"dap2_sclk_pa3",

						"dap2_din_pa4",

						"dap2_dout_pa5";

				nvidia,function = "i2s1";

				nvidia,pull = <0>;

				nvidia,tristate = <0>;

			};

		};

	};
@@ -92,6 +101,20 @@ 


	i2c@7000d000 {

		clock-frequency = <100000>;



		wm8903: wm8903@1a {

			compatible = "wlf,wm8903";

			reg = <0x1a>;

			interrupt-parent = <&gpio>;

			interrupts = <179 0x04>; /* gpio PW3 */



			gpio-controller;

			#gpio-cells = <2>;



			micdet-cfg = <0>;

			micdet-delay = <100>;

			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;

		};

	};



	sdhci@78000000 {
@@ -111,4 +134,44 @@ 
	sdhci@78000400 {

		support-8bit;

	};



	ahub@70080000 {

		i2s@70080300 {

			status = "disable";

		};



		i2s@70080500 {

			status = "disable";

		};



		i2s@70080600 {

			status = "disable";

		};



		i2s@70080700 {

			status = "disable";

		};

	};



	sound {

		compatible = "nvidia,tegra-audio-wm8903-cardhu",

			     "nvidia,tegra-audio-wm8903";

		nvidia,model = "NVIDIA Tegra Cardhu";



		nvidia,audio-routing =

			"Headphone Jack", "HPOUTR",

			"Headphone Jack", "HPOUTL",

			"Int Spk", "ROP",

			"Int Spk", "RON",

			"Int Spk", "LOP",

			"Int Spk", "LON",

			"Mic Jack", "MICBIAS",

			"IN1L", "Mic Jack";



		nvidia,i2s-controller = <&tegra_i2s1>;

		nvidia,audio-codec = <&wm8903>;



		nvidia,spkr-en-gpios = <&wm8903 2 0>;

		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */

	};

};

arch/arm/boot/dts/tegra30.dtsi

+41 −0
Original line number Diff line number Diff line
@@ -183,4 +183,45 @@ 
		reg = < 0x70000868 0xd0     /* Pad control registers */

			0x70003000 0x3e0 >; /* Mux registers */

	};



	ahub {

		compatible = "nvidia,tegra30-ahub";

		reg = <0x70080000 0x200 0x70080200 0x100>;

		interrupts = < 0 103 0x04 >;

		nvidia,dma-request-selector = <&apbdma 1>;



		ranges;

		#address-cells = <1>;

		#size-cells = <1>;



		tegra_i2s0: i2s@70080300 {

			compatible = "nvidia,tegra30-i2s";

			reg = <0x70080300 0x100>;

			nvidia,ahub-cif-ids = <4 4>;

		};



		tegra_i2s1: i2s@70080400 {

			compatible = "nvidia,tegra30-i2s";

			reg = <0x70080400 0x100>;

			nvidia,ahub-cif-ids = <5 5>;

		};



		tegra_i2s2: i2s@70080500 {

			compatible = "nvidia,tegra30-i2s";

			reg = <0x70080500 0x100>;

			nvidia,ahub-cif-ids = <6 6>;

		};



		tegra_i2s3: i2s@70080600 {

			compatible = "nvidia,tegra30-i2s";

			reg = <0x70080600 0x100>;

			nvidia,ahub-cif-ids = <7 7>;

		};



		tegra_i2s4: i2s@70080700 {

			compatible = "nvidia,tegra30-i2s";

			reg = <0x70080700 0x100>;

			nvidia,ahub-cif-ids = <8 8>;

		};

	};

};

arch/arm/mach-tegra/board-dt-tegra30.c

+10 −0
Original line number Diff line number Diff line
@@ -51,12 +51,22 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { 
	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C500, "tegra-i2c.2", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000C700, "tegra-i2c.3", NULL),

	OF_DEV_AUXDATA("nvidia,tegra20-i2c", 0x7000D000, "tegra-i2c.4", NULL),

	OF_DEV_AUXDATA("nvidia,tegra30-ahub", 0x70080000, "tegra30-ahub", NULL),

	{}

};



static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {

	/* name		parent		rate		enabled */

	{ "uarta",	"pll_p",	408000000,	true },

	{ "pll_a",	"pll_p_out1",	564480000,	true },

	{ "pll_a_out0",	"pll_a",	11289600,	true },

	{ "extern1",	"pll_a_out0",	0,		true },

	{ "clk_out_1",	"extern1",	0,		true },

	{ "i2s0",	"pll_a_out0",	11289600,	false},

	{ "i2s1",	"pll_a_out0",	11289600,	false},

	{ "i2s2",	"pll_a_out0",	11289600,	false},

	{ "i2s3",	"pll_a_out0",	11289600,	false},

	{ "i2s4",	"pll_a_out0",	11289600,	false},

	{ NULL,		NULL,		0,		0},

};

arch/arm/mach-tegra/common.c

+12 −0
Original line number Diff line number Diff line
@@ -95,6 +95,17 @@ static __initdata struct tegra_clk_init_table tegra20_clk_init_table[] = { 
};

#endif



#ifdef CONFIG_ARCH_TEGRA_3x_SOC

static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = {

	/* name		parent		rate		enabled */

	{ "clk_m",	NULL,		0,		true },

	{ "pll_p",	"clk_m",	408000000,	true },

	{ "pll_p_out1",	"pll_p",	9600000,	true },

	{ NULL,		NULL,		0,		0},

};

#endif





static void __init tegra_init_cache(u32 tag_latency, u32 data_latency)

{

#ifdef CONFIG_CACHE_L2X0
@@ -129,6 +140,7 @@ void __init tegra30_init_early(void) 
{

	tegra_init_fuse();

	tegra30_init_clocks();

	tegra_clk_init_from_table(tegra30_clk_init_table);

	tegra_init_cache(0x441, 0x551);

	tegra_pmc_init();

	tegra_powergate_init();

arch/arm/mach-tegra/tegra30_clocks.c

+9 −0
Original line number Diff line number Diff line
@@ -3015,6 +3015,15 @@ struct clk_duplicate tegra_clk_duplicates[] = { 
	CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),

	CLK_DUPLICATE("twd", "smp_twd", NULL),

	CLK_DUPLICATE("vcp", "nvavp", "vcp"),

	CLK_DUPLICATE("i2s0", NULL, "i2s0"),

	CLK_DUPLICATE("i2s1", NULL, "i2s1"),

	CLK_DUPLICATE("i2s2", NULL, "i2s2"),

	CLK_DUPLICATE("i2s3", NULL, "i2s3"),

	CLK_DUPLICATE("i2s4", NULL, "i2s4"),

	CLK_DUPLICATE("dam0", NULL, "dam0"),

	CLK_DUPLICATE("dam1", NULL, "dam1"),

	CLK_DUPLICATE("dam2", NULL, "dam2"),

	CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),

};



struct clk *tegra_ptr_clks[] = {