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Commit 799a75ab authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Simon Horman
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arm64: dts: r8a7795: Add Cortex-A53 CPU cores 



This patch adds Cortex-A53 CPU cores to r8a7795 SoC for a total of 8
cores (4 x Cortex-A57 + 4 x Cortex-A53).

Based on work by Takeshi Kihara and Dirk Behme.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: default avatarSimon Horman <horms+renesas@verge.net.au>
parent 6d50bb89

arch/arm64/boot/dts/renesas/r8a7795.dtsi

+41 −5
Original line number Diff line number Diff line
@@ -73,6 +73,42 @@ 
			enable-method = "psci";

		};



		a53_0: cpu@100 {

			compatible = "arm,cortex-a53", "arm,armv8";

			reg = <0x100>;

			device_type = "cpu";

			power-domains = <&sysc R8A7795_PD_CA53_CPU0>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		a53_1: cpu@101 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x101>;

			device_type = "cpu";

			power-domains = <&sysc R8A7795_PD_CA53_CPU1>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		a53_2: cpu@102 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x102>;

			device_type = "cpu";

			power-domains = <&sysc R8A7795_PD_CA53_CPU2>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		a53_3: cpu@103 {

			compatible = "arm,cortex-a53","arm,armv8";

			reg = <0x103>;

			device_type = "cpu";

			power-domains = <&sysc R8A7795_PD_CA53_CPU3>;

			next-level-cache = <&L2_CA53>;

			enable-method = "psci";

		};



		L2_CA57: cache-controller@0 {

			compatible = "cache";

			reg = <0>;
@@ -166,7 +202,7 @@ 
			      <0x0 0xf1040000 0 0x20000>,

			      <0x0 0xf1060000 0 0x20000>;

			interrupts = <GIC_PPI 9

					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;

					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;

			clocks = <&cpg CPG_MOD 408>;

			clock-names = "clk";

			power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
@@ -307,13 +343,13 @@ 
		timer {

			compatible = "arm,armv8-timer";

			interrupts = <GIC_PPI 13

					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 14

					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 11

					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,

				     <GIC_PPI 10

					(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;

					(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;

		};



		cpg: clock-controller@e6150000 {