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Commit 7936e914 authored by Jean-Philippe Brucker's avatar Jean-Philippe Brucker Committed by Marc Zyngier
Browse files

irqchip/gic-v3: Refactor the arm64 specific parts 



This patch moves the GICv3 system register access helpers to
arch/arm64/. Their 32bit counterparts will need to use mrc/mcr accesses
instead of mrs_s/msr_s.

[maz: fixed conflict with Cavium erratum handling]
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarJean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
parent ee5f7d64

arch/arm64/include/asm/arch_gicv3.h

0 → 100644
+162 −0
Original line number Original line Diff line number Diff line 
/*

 * arch/arm64/include/asm/arch_gicv3.h

 *

 * Copyright (C) 2015 ARM Ltd.

 *

 * This program is free software: you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/>.

 */

#ifndef __ASM_ARCH_GICV3_H

#define __ASM_ARCH_GICV3_H



#include <asm/sysreg.h>



#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)

#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)

#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)

#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)

#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)

#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)

#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)

#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)



#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)



/*

 * System register definitions

 */

#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)

#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)

#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)

#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)

#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)

#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)

#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)



#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)

#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)



#define ICH_LR0_EL2			__LR0_EL2(0)

#define ICH_LR1_EL2			__LR0_EL2(1)

#define ICH_LR2_EL2			__LR0_EL2(2)

#define ICH_LR3_EL2			__LR0_EL2(3)

#define ICH_LR4_EL2			__LR0_EL2(4)

#define ICH_LR5_EL2			__LR0_EL2(5)

#define ICH_LR6_EL2			__LR0_EL2(6)

#define ICH_LR7_EL2			__LR0_EL2(7)

#define ICH_LR8_EL2			__LR8_EL2(0)

#define ICH_LR9_EL2			__LR8_EL2(1)

#define ICH_LR10_EL2			__LR8_EL2(2)

#define ICH_LR11_EL2			__LR8_EL2(3)

#define ICH_LR12_EL2			__LR8_EL2(4)

#define ICH_LR13_EL2			__LR8_EL2(5)

#define ICH_LR14_EL2			__LR8_EL2(6)

#define ICH_LR15_EL2			__LR8_EL2(7)



#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)

#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)

#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)

#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)

#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)



#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)

#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)

#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)

#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)

#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)



#ifndef __ASSEMBLY__



#include <linux/stringify.h>



/* Low level accessors */



static inline void gic_write_eoir(u64 irq)

{

	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));

	isb();

}



static inline void gic_write_dir(u64 irq)

{

	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));

	isb();

}



static inline u64 gic_read_iar_common(void)

{

	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	return irqstat;

}



/*

 * Cavium ThunderX erratum 23154

 *

 * The gicv3 of ThunderX requires a modified version for reading the

 * IAR status to ensure data synchronization (access to icc_iar1_el1

 * is not sync'ed before and after).

 */

static inline u64 gic_read_iar_cavium_thunderx(void)

{

	u64 irqstat;



	asm volatile(

		"nop;nop;nop;nop\n\t"

		"nop;nop;nop;nop\n\t"

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"

		"nop;nop;nop;nop"

		: "=r" (irqstat));

	mb();



	return irqstat;

}



static inline void gic_write_pmr(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));

}



static inline void gic_write_ctlr(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));

	isb();

}



static inline void gic_write_grpen1(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));

	isb();

}



static inline void gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

}



static inline u64 gic_read_sre(void)

{

	u64 val;



	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	return val;

}



static inline void gic_write_sre(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));

	isb();

}



#endif /* __ASSEMBLY__ */

#endif /* __ASM_ARCH_GICV3_H */

drivers/irqchip/irq-gic-v3.c

+4 −53
Original line number Original line Diff line number Diff line
@@ -108,37 +108,7 @@ static void gic_redist_wait_for_rwp(void) 
	gic_do_wait_for_rwp(gic_data_rdist_rd_base());

	gic_do_wait_for_rwp(gic_data_rdist_rd_base());

}

}





/* Low level accessors */

#ifdef CONFIG_ARM64

static u64 gic_read_iar_common(void)

{

	u64 irqstat;



	asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat));

	return irqstat;

}



/*

 * Cavium ThunderX erratum 23154

 *

 * The gicv3 of ThunderX requires a modified version for reading the

 * IAR status to ensure data synchronization (access to icc_iar1_el1

 * is not sync'ed before and after).

 */

static u64 gic_read_iar_cavium_thunderx(void)

{

	u64 irqstat;



	asm volatile(

		"nop;nop;nop;nop\n\t"

		"nop;nop;nop;nop\n\t"

		"mrs_s %0, " __stringify(ICC_IAR1_EL1) "\n\t"

		"nop;nop;nop;nop"

		: "=r" (irqstat));

	mb();



	return irqstat;

}



static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);

static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx);





static u64 __maybe_unused gic_read_iar(void)

static u64 __maybe_unused gic_read_iar(void)
@@ -148,28 +118,7 @@ static u64 __maybe_unused gic_read_iar(void) 
	else

	else

		return gic_read_iar_common();

		return gic_read_iar_common();

}

}



#endif

static void __maybe_unused gic_write_pmr(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val));

}



static void __maybe_unused gic_write_ctlr(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val));

	isb();

}



static void __maybe_unused gic_write_grpen1(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val));

	isb();

}



static void __maybe_unused gic_write_sgi1r(u64 val)

{

	asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val));

}





static void gic_enable_redist(bool enable)

static void gic_enable_redist(bool enable)

{

{
@@ -856,8 +805,10 @@ static const struct irq_domain_ops gic_irq_domain_ops = { 




static void gicv3_enable_quirks(void)

static void gicv3_enable_quirks(void)

{

{

#ifdef CONFIG_ARM64

	if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))

	if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154))

		static_branch_enable(&is_cavium_thunderx);

		static_branch_enable(&is_cavium_thunderx);

#endif

}

}





static int __init gic_of_init(struct device_node *node, struct device_node *parent)

static int __init gic_of_init(struct device_node *node, struct device_node *parent)

include/linux/irqchip/arm-gic-v3.h

+9 −79
Original line number Original line Diff line number Diff line
@@ -18,8 +18,6 @@ 
#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H

#ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H

#define __LINUX_IRQCHIP_ARM_GIC_V3_H

#define __LINUX_IRQCHIP_ARM_GIC_V3_H





#include <asm/sysreg.h>



/*

/*

 * Distributor registers. We assume we're running non-secure, with ARE

 * Distributor registers. We assume we're running non-secure, with ARE

 * being set. Secure-only and non-ARE registers are not described.

 * being set. Secure-only and non-ARE registers are not described.
@@ -293,19 +291,8 @@ 
#define ICH_VMCR_PMR_SHIFT		24

#define ICH_VMCR_PMR_SHIFT		24

#define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)

#define ICH_VMCR_PMR_MASK		(0xffUL << ICH_VMCR_PMR_SHIFT)





#define ICC_EOIR1_EL1			sys_reg(3, 0, 12, 12, 1)

#define ICC_DIR_EL1			sys_reg(3, 0, 12, 11, 1)

#define ICC_IAR1_EL1			sys_reg(3, 0, 12, 12, 0)

#define ICC_SGI1R_EL1			sys_reg(3, 0, 12, 11, 5)

#define ICC_PMR_EL1			sys_reg(3, 0, 4, 6, 0)

#define ICC_CTLR_EL1			sys_reg(3, 0, 12, 12, 4)

#define ICC_SRE_EL1			sys_reg(3, 0, 12, 12, 5)

#define ICC_GRPEN1_EL1			sys_reg(3, 0, 12, 12, 7)



#define ICC_IAR1_EL1_SPURIOUS		0x3ff

#define ICC_IAR1_EL1_SPURIOUS		0x3ff





#define ICC_SRE_EL2			sys_reg(3, 4, 12, 9, 5)



#define ICC_SRE_EL2_SRE			(1 << 0)

#define ICC_SRE_EL2_SRE			(1 << 0)

#define ICC_SRE_EL2_ENABLE		(1 << 3)

#define ICC_SRE_EL2_ENABLE		(1 << 3)
@@ -321,54 +308,10 @@ 
#define ICC_SGI1R_AFFINITY_3_SHIFT	48

#define ICC_SGI1R_AFFINITY_3_SHIFT	48

#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)

#define ICC_SGI1R_AFFINITY_3_MASK	(0xffULL << ICC_SGI1R_AFFINITY_1_SHIFT)





/*

#include <asm/arch_gicv3.h>

 * System register definitions

 */

#define ICH_VSEIR_EL2			sys_reg(3, 4, 12, 9, 4)

#define ICH_HCR_EL2			sys_reg(3, 4, 12, 11, 0)

#define ICH_VTR_EL2			sys_reg(3, 4, 12, 11, 1)

#define ICH_MISR_EL2			sys_reg(3, 4, 12, 11, 2)

#define ICH_EISR_EL2			sys_reg(3, 4, 12, 11, 3)

#define ICH_ELSR_EL2			sys_reg(3, 4, 12, 11, 5)

#define ICH_VMCR_EL2			sys_reg(3, 4, 12, 11, 7)



#define __LR0_EL2(x)			sys_reg(3, 4, 12, 12, x)

#define __LR8_EL2(x)			sys_reg(3, 4, 12, 13, x)



#define ICH_LR0_EL2			__LR0_EL2(0)

#define ICH_LR1_EL2			__LR0_EL2(1)

#define ICH_LR2_EL2			__LR0_EL2(2)

#define ICH_LR3_EL2			__LR0_EL2(3)

#define ICH_LR4_EL2			__LR0_EL2(4)

#define ICH_LR5_EL2			__LR0_EL2(5)

#define ICH_LR6_EL2			__LR0_EL2(6)

#define ICH_LR7_EL2			__LR0_EL2(7)

#define ICH_LR8_EL2			__LR8_EL2(0)

#define ICH_LR9_EL2			__LR8_EL2(1)

#define ICH_LR10_EL2			__LR8_EL2(2)

#define ICH_LR11_EL2			__LR8_EL2(3)

#define ICH_LR12_EL2			__LR8_EL2(4)

#define ICH_LR13_EL2			__LR8_EL2(5)

#define ICH_LR14_EL2			__LR8_EL2(6)

#define ICH_LR15_EL2			__LR8_EL2(7)



#define __AP0Rx_EL2(x)			sys_reg(3, 4, 12, 8, x)

#define ICH_AP0R0_EL2			__AP0Rx_EL2(0)

#define ICH_AP0R1_EL2			__AP0Rx_EL2(1)

#define ICH_AP0R2_EL2			__AP0Rx_EL2(2)

#define ICH_AP0R3_EL2			__AP0Rx_EL2(3)



#define __AP1Rx_EL2(x)			sys_reg(3, 4, 12, 9, x)

#define ICH_AP1R0_EL2			__AP1Rx_EL2(0)

#define ICH_AP1R1_EL2			__AP1Rx_EL2(1)

#define ICH_AP1R2_EL2			__AP1Rx_EL2(2)

#define ICH_AP1R3_EL2			__AP1Rx_EL2(3)





#ifndef __ASSEMBLY__

#ifndef __ASSEMBLY__





#include <linux/stringify.h>

#include <asm/msi.h>



/*

/*

 * We need a value to serve as a irq-type for LPIs. Choose one that will

 * We need a value to serve as a irq-type for LPIs. Choose one that will

 * hopefully pique the interest of the reviewer.

 * hopefully pique the interest of the reviewer.
@@ -386,39 +329,26 @@ struct rdists { 
	u64			flags;

	u64			flags;

};

};





static inline void gic_write_eoir(u64 irq)

struct irq_domain;

{

int its_cpu_init(void);

	asm volatile("msr_s " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));

int its_init(struct device_node *node, struct rdists *rdists,

	isb();

	     struct irq_domain *domain);

}



static inline void gic_write_dir(u64 irq)

{

	asm volatile("msr_s " __stringify(ICC_DIR_EL1) ", %0" : : "r" (irq));

	isb();

}





static inline bool gic_enable_sre(void)

static inline bool gic_enable_sre(void)

{

{

	u64 val;

	u32 val;





	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));

	val = gic_read_sre();

	if (val & ICC_SRE_EL1_SRE)

	if (val & ICC_SRE_EL1_SRE)

		return true;

		return true;





	val |= ICC_SRE_EL1_SRE;

	val |= ICC_SRE_EL1_SRE;

	asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val));

	gic_write_sre(val);

	isb();

	val = gic_read_sre();

	asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val));





	return !!(val & ICC_SRE_EL1_SRE);

	return !!(val & ICC_SRE_EL1_SRE);

}

}





struct irq_domain;

int its_cpu_init(void);

int its_init(struct device_node *node, struct rdists *rdists,

	     struct irq_domain *domain);



#endif

#endif





#endif
 
#endif