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Commit 79271807 authored by Stefan Schake's avatar Stefan Schake Committed by Eric Anholt
Browse files

drm/vc4: Move CRTC state to header 



We need to access the channel for configuring our CTM hardware.

Signed-off-by: default avatarStefan Schake <stschake@gmail.com>
Signed-off-by: default avatarEric Anholt <eric@anholt.net>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Link: https://patchwork.freedesktop.org/patch/msgid/1523479755-20812-4-git-send-email-stschake@gmail.com
parent 640e0c79

drivers/gpu/drm/vc4/vc4_crtc.c

+0 −33
Original line number Diff line number Diff line
@@ -42,51 +42,18 @@ 
#include "vc4_drv.h"

#include "vc4_regs.h"



struct vc4_crtc {

	struct drm_crtc base;

	const struct vc4_crtc_data *data;

	void __iomem *regs;



	/* Timestamp at start of vblank irq - unaffected by lock delays. */

	ktime_t t_vblank;



	/* Which HVS channel we're using for our CRTC. */

	int channel;



	u8 lut_r[256];

	u8 lut_g[256];

	u8 lut_b[256];

	/* Size in pixels of the COB memory allocated to this CRTC. */

	u32 cob_size;



	struct drm_pending_vblank_event *event;

};



struct vc4_crtc_state {

	struct drm_crtc_state base;

	/* Dlist area for this CRTC configuration. */

	struct drm_mm_node mm;

};



static inline struct vc4_crtc *

to_vc4_crtc(struct drm_crtc *crtc)

{

	return (struct vc4_crtc *)crtc;

}



static inline struct vc4_crtc_state *

to_vc4_crtc_state(struct drm_crtc_state *crtc_state)

{

	return (struct vc4_crtc_state *)crtc_state;

}



struct vc4_crtc_data {

	/* Which channel of the HVS this pixelvalve sources from. */

	int hvs_channel;



	enum vc4_encoder_type encoder_types[4];

};



#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))

#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))

drivers/gpu/drm/vc4/vc4_drv.h

+33 −0
Original line number Diff line number Diff line
@@ -392,6 +392,39 @@ to_vc4_encoder(struct drm_encoder *encoder) 
	return container_of(encoder, struct vc4_encoder, base);

}



struct vc4_crtc_data {

	/* Which channel of the HVS this pixelvalve sources from. */

	int hvs_channel;



	enum vc4_encoder_type encoder_types[4];

};



struct vc4_crtc {

	struct drm_crtc base;

	const struct vc4_crtc_data *data;

	void __iomem *regs;



	/* Timestamp at start of vblank irq - unaffected by lock delays. */

	ktime_t t_vblank;



	/* Which HVS channel we're using for our CRTC. */

	int channel;



	u8 lut_r[256];

	u8 lut_g[256];

	u8 lut_b[256];

	/* Size in pixels of the COB memory allocated to this CRTC. */

	u32 cob_size;



	struct drm_pending_vblank_event *event;

};



static inline struct vc4_crtc *

to_vc4_crtc(struct drm_crtc *crtc)

{

	return (struct vc4_crtc *)crtc;

}



#define V3D_READ(offset) readl(vc4->v3d->regs + offset)

#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset)

#define HVS_READ(offset) readl(vc4->hvs->regs + offset)