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Commit 78c10e55 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus 

Pull MIPS updates from Ralf Baechle:

 - Improvements to the tlb_dump code
 - KVM fixes
 - Add support for appended DTB
 - Minor improvements to the R12000 support
 - Minor improvements to the R12000 support
 - Various platform improvments for BCM47xx
 - The usual pile of minor cleanups
 - A number of BPF fixes and improvments
 - Some improvments to the support for R3000 and DECstations
 - Some improvments to the ATH79 platform support
 - A major patchset for the JZ4740 SOC adding support for the CI20 platform
 - Add support for the Pistachio SOC
 - Minor BMIPS/BCM63xx platform support improvments.
 - Avoid "SYNC 0" as memory barrier when unlocking spinlocks
 - Add support for the XWR-1750 board.
 - Paul's __cpuinit/__cpuinitdata cleanups.
 - New Malta CPU board support large memory so enable ZONE_DMA32.

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (131 commits)
  MIPS: spinlock: Adjust arch_spin_lock back-off time
  MIPS: asmmacro: Ensure 64-bit FP registers are used with MSA
  MIPS: BCM47xx: Simplify handling SPROM revisions
  MIPS: Cobalt Don't use module_init in non-modular MTD registration.
  MIPS: BCM47xx: Move NVRAM driver to the drivers/firmware/
  MIPS: use for_each_sg()
  MIPS: BCM47xx: Don't select BCMA_HOST_PCI
  MIPS: BCM47xx: Add helper variable for storing NVRAM length
  MIPS: IRQ/IP27: Move IRQ allocation API to platform code.
  MIPS: Replace smp_mb with release barrier function in unlocks.
  MIPS: i8259: DT support
  MIPS: Malta: Basic DT plumbing
  MIPS: include errno.h for ENODEV in mips-cm.h
  MIPS: Define GCR_GIC_STATUS register fields
  MIPS: BPF: Introduce BPF ASM helpers
  MIPS: BPF: Use BPF register names to describe the ABI
  MIPS: BPF: Move register definition to the BPF header
  MIPS: net: BPF: Replace RSIZE with SZREG
  MIPS: BPF: Free up some callee-saved registers
  MIPS: Xtalk: Update xwidget.h with known Xtalk device numbers
  ...
parents d2c3ac7e 9ff897c4

Documentation/devicetree/bindings/clock/ingenic,cgu.txt

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Ingenic SoC CGU binding



The CGU in an Ingenic SoC provides all the clocks generated on-chip. It

typically includes a variety of PLLs, multiplexers, dividers & gates in order

to provide many different clock signals derived from only 2 external source

clocks.



Required properties:

- compatible : Should be "ingenic,<soctype>-cgu".

  For example "ingenic,jz4740-cgu" or "ingenic,jz4780-cgu".

- reg : The address & length of the CGU registers.

- clocks : List of phandle & clock specifiers for clocks external to the CGU.

  Two such external clocks should be specified - first the external crystal

  "ext" and second the RTC clock source "rtc".

- clock-names : List of name strings for the external clocks.

- #clock-cells: Should be 1.

  Clock consumers specify this argument to identify a clock. The valid values

  may be found in <dt-bindings/clock/<soctype>-cgu.h>.



Example SoC include file:



/ {

	cgu: jz4740-cgu {

		compatible = "ingenic,jz4740-cgu";

		reg = <0x10000000 0x100>;

		#clock-cells = <1>;

	};



	uart0: serial@10030000 {

		clocks = <&cgu JZ4740_CLK_UART0>;

	};

};



Example board file:



/ {

	ext: clock@0 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <12000000>;

	};



	rtc: clock@1 {

		compatible = "fixed-clock";

		#clock-cells = <0>;

		clock-frequency = <32768>;

	};



	&cgu {

		clocks = <&ext> <&rtc>;

		clock-names: "ext", "rtc";

	};

};

Documentation/devicetree/bindings/clock/qca,ath79-pll.txt

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Binding for Qualcomm Atheros AR7xxx/AR9XXX PLL controller



The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.



Required Properties:

- compatible: has to be "qca,<soctype>-cpu-intc" and one of the following

  fallbacks:

  - "qca,ar7100-pll"

  - "qca,ar7240-pll"

  - "qca,ar9130-pll"

  - "qca,ar9330-pll"

  - "qca,ar9340-pll"

  - "qca,qca9550-pll"

- reg: Base address and size of the controllers memory area

- clock-names: Name of the input clock, has to be "ref"

- clocks: phandle of the external reference clock

- #clock-cells: has to be one



Optional properties:

- clock-output-names: should be "cpu", "ddr", "ahb"



Example:



	memory-controller@18050000 {

		compatible = "qca,ar9132-ppl", "qca,ar9130-pll";

		reg = <0x18050000 0x20>;



		clock-names = "ref";

		clocks = <&extosc>;



		#clock-cells = <1>;

		clock-output-names = "cpu", "ddr", "ahb";

	};

Documentation/devicetree/bindings/gpio/gpio-ath79.txt

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Binding for Qualcomm Atheros AR7xxx/AR9xxx GPIO controller



Required properties:

- compatible: has to be "qca,<soctype>-gpio" and one of the following

  fallbacks:

  - "qca,ar7100-gpio"

  - "qca,ar9340-gpio"

- reg: Base address and size of the controllers memory area

- gpio-controller : Marks the device node as a GPIO controller.

- #gpio-cells : Should be two. The first cell is the pin number and the

  second cell is used to specify optional parameters.

- ngpios: Should be set to the number of GPIOs available on the SoC.



Optional properties:

- interrupt-parent: phandle of the parent interrupt controller.

- interrupts: Interrupt specifier for the controllers interrupt.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 2



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.



Example:



	gpio@18040000 {

		compatible = "qca,ar9132-gpio", "qca,ar7100-gpio";

		reg = <0x18040000 0x30>;

		interrupts = <2>;



		ngpios = <22>;



		gpio-controller;

		#gpio-cells = <2>;



		interrupt-controller;

		#interrupt-cells = <2>;

	};

Documentation/devicetree/bindings/interrupt-controller/ingenic,intc.txt

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Ingenic SoC Interrupt Controller



Required properties:



- compatible : should be "ingenic,<socname>-intc". Valid strings are:

    ingenic,jz4740-intc

    ingenic,jz4770-intc

    ingenic,jz4775-intc

    ingenic,jz4780-intc

- reg : Specifies base physical address and size of the registers.

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode an

  interrupt source. The value shall be 1.

- interrupt-parent : phandle of the CPU interrupt controller.

- interrupts : Specifies the CPU interrupt the controller is connected to.



Example:



intc: interrupt-controller@10001000 {

	compatible = "ingenic,jz4740-intc";

	reg = <0x10001000 0x14>;



	interrupt-controller;

	#interrupt-cells = <1>;



	interrupt-parent = <&cpuintc>;

	interrupts = <2>;

};

Documentation/devicetree/bindings/interrupt-controller/qca,ath79-cpu-intc.txt

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Binding for Qualcomm Atheros AR7xxx/AR9XXX CPU interrupt controller



On most SoC the IRQ controller need to flush the DDR FIFO before running

the interrupt handler of some devices. This is configured using the

qca,ddr-wb-channels and qca,ddr-wb-channel-interrupts properties.



Required Properties:



- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-cpu-intc"

  as fallback

- interrupt-controller : Identifies the node as an interrupt controller

- #interrupt-cells : Specifies the number of cells needed to encode interrupt

		     source, should be 1 for intc



Please refer to interrupts.txt in this directory for details of the common

Interrupt Controllers bindings used by client devices.



Optional Properties:



- qca,ddr-wb-channel-interrupts: List of the interrupts needing a write

  buffer flush

- qca,ddr-wb-channels: List of phandles to the write buffer channels for

  each interrupt. If qca,ddr-wb-channel-interrupts is not present the interrupt

  default to the entry's index.



Example:



	interrupt-controller {

		compatible = "qca,ar9132-cpu-intc", "qca,ar7100-cpu-intc";



		interrupt-controller;

		#interrupt-cells = <1>;



		qca,ddr-wb-channel-interrupts = <2>, <3>, <4>, <5>;

		qca,ddr-wb-channels = <&ddr_ctrl 3>, <&ddr_ctrl 2>,

					<&ddr_ctrl 0>, <&ddr_ctrl 1>;

	};



	...



	ddr_ctrl: memory-controller@18000000 {

		...

		#qca,ddr-wb-channel-cells = <1>;

	};