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Commit 78babc16 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: convert iova to 64b 



For a5xx the gpu is 64b so we need to change iova to 64b everywhere.  On
the display side, iova is still 32b so it can ignore the upper bits.
(Although all the armv8 devices have an iommu that can map 64b pa to 32b
iova.)

Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent c83ea576

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+1 −1
Original line number Diff line number Diff line
@@ -153,7 +153,7 @@ struct adreno_gpu { 
	// different for z180..

	struct adreno_rbmemptrs *memptrs;

	struct drm_gem_object *memptrs_bo;

	uint32_t memptrs_iova;

	uint64_t memptrs_iova;



	/*

	 * Register offsets are different between some GPUs.

drivers/gpu/drm/msm/dsi/dsi_host.c

+2 −2
Original line number Diff line number Diff line
@@ -981,7 +981,7 @@ static int dsi_tx_buf_alloc(struct msm_dsi_host *msm_host, int size) 
	struct drm_device *dev = msm_host->dev;

	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;

	int ret;

	u32 iova;

	uint64_t iova;



	if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {

		mutex_lock(&dev->struct_mutex);
@@ -1146,7 +1146,7 @@ static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 
{

	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;

	int ret;

	u32 dma_base;

	uint64_t dma_base;

	bool triggered;



	if (cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) {

drivers/gpu/drm/msm/mdp/mdp4/mdp4_crtc.c

+2 −2
Original line number Diff line number Diff line
@@ -373,7 +373,7 @@ static void update_cursor(struct drm_crtc *crtc) 
	if (mdp4_crtc->cursor.stale) {

		struct drm_gem_object *next_bo = mdp4_crtc->cursor.next_bo;

		struct drm_gem_object *prev_bo = mdp4_crtc->cursor.scanout_bo;

		uint32_t iova = mdp4_crtc->cursor.next_iova;

		uint64_t iova = mdp4_crtc->cursor.next_iova;



		if (next_bo) {

			/* take a obj ref + iova ref when we start scanning out: */
@@ -418,7 +418,7 @@ static int mdp4_crtc_cursor_set(struct drm_crtc *crtc, 
	struct drm_device *dev = crtc->dev;

	struct drm_gem_object *cursor_bo, *old_bo;

	unsigned long flags;

	uint32_t iova;

	uint64_t iova;

	int ret;



	if ((width > CURSOR_WIDTH) || (height > CURSOR_HEIGHT)) {

drivers/gpu/drm/msm/mdp/mdp4/mdp4_kms.h

+1 −1
Original line number Diff line number Diff line
@@ -51,7 +51,7 @@ struct mdp4_kms { 


	/* empty/blank cursor bo to use when cursor is "disabled" */

	struct drm_gem_object *blank_cursor_bo;

	uint32_t blank_cursor_iova;

	uint64_t blank_cursor_iova;

};

#define to_mdp4_kms(x) container_of(x, struct mdp4_kms, base)

drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c

+2 −1
Original line number Diff line number Diff line
@@ -489,7 +489,8 @@ static int mdp5_crtc_cursor_set(struct drm_crtc *crtc, 
	struct drm_device *dev = crtc->dev;

	struct mdp5_kms *mdp5_kms = get_kms(crtc);

	struct drm_gem_object *cursor_bo, *old_bo = NULL;

	uint32_t blendcfg, cursor_addr, stride;

	uint32_t blendcfg, stride;

	uint64_t cursor_addr;

	int ret, lm;

	enum mdp5_cursor_alpha cur_alpha = CURSOR_ALPHA_PER_PIXEL;

	uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0);