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Commit 780fc564 authored by Kirill A. Shutemov's avatar Kirill A. Shutemov Committed by Linus Torvalds
Browse files

powerpc: drop _PAGE_FILE and pte_file()-related helpers 



We've replaced remap_file_pages(2) implementation with emulation.  Nobody
creates non-linear mapping anymore.

Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 160cc266

arch/powerpc/include/asm/pgtable-ppc32.h

+2 −7
Original line number Original line Diff line number Diff line
@@ -333,8 +333,8 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) 
/*

/*

 * Encode and decode a swap entry.

 * Encode and decode a swap entry.

 * Note that the bits we use in a PTE for representing a swap entry

 * Note that the bits we use in a PTE for representing a swap entry

 * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the

 * must not include the _PAGE_PRESENT bit or the _PAGE_HASHPTE bit (if used).

 *_PAGE_HASHPTE bit (if used).  -- paulus

 *   -- paulus

 */

 */

#define __swp_type(entry)		((entry).val & 0x1f)

#define __swp_type(entry)		((entry).val & 0x1f)

#define __swp_offset(entry)		((entry).val >> 5)

#define __swp_offset(entry)		((entry).val >> 5)
@@ -342,11 +342,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) 
#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })

#define __pte_to_swp_entry(pte)		((swp_entry_t) { pte_val(pte) >> 3 })

#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })

#define __swp_entry_to_pte(x)		((pte_t) { (x).val << 3 })





/* Encode and decode a nonlinear file mapping entry */

#define PTE_FILE_MAX_BITS	29

#define pte_to_pgoff(pte)	(pte_val(pte) >> 3)

#define pgoff_to_pte(off)	((pte_t) { ((off) << 3) | _PAGE_FILE })



#ifndef CONFIG_PPC_4K_PAGES

#ifndef CONFIG_PPC_4K_PAGES

void pgtable_cache_init(void);

void pgtable_cache_init(void);

#else

#else

arch/powerpc/include/asm/pgtable-ppc64.h

+1 −4
Original line number Original line Diff line number Diff line
@@ -352,9 +352,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry) 
#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})

#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})

#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})

#define __pte_to_swp_entry(pte)	((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})

#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })

#define __swp_entry_to_pte(x)	((pte_t) { (x).val << PTE_RPN_SHIFT })

#define pte_to_pgoff(pte)	(pte_val(pte) >> PTE_RPN_SHIFT)

#define pgoff_to_pte(off)	((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})

#define PTE_FILE_MAX_BITS	(BITS_PER_LONG - PTE_RPN_SHIFT)





void pgtable_cache_add(unsigned shift, void (*ctor)(void *));

void pgtable_cache_add(unsigned shift, void (*ctor)(void *));

void pgtable_cache_init(void);

void pgtable_cache_init(void);
@@ -389,7 +386,7 @@ void pgtable_cache_init(void); 
 * The last three bits are intentionally left to zero. This memory location

 * The last three bits are intentionally left to zero. This memory location

 * are also used as normal page PTE pointers. So if we have any pointers

 * are also used as normal page PTE pointers. So if we have any pointers

 * left around while we collapse a hugepage, we need to make sure

 * left around while we collapse a hugepage, we need to make sure

 * _PAGE_PRESENT and _PAGE_FILE bits of that are zero when we look at them

 * _PAGE_PRESENT bit of that is zero when we look at them

 */

 */

static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)

static inline unsigned int hpte_valid(unsigned char *hpte_slot_array, int index)

{

{

arch/powerpc/include/asm/pgtable.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -34,7 +34,6 @@ static inline int pte_write(pte_t pte) 
{	return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; }

{	return (pte_val(pte) & (_PAGE_RW | _PAGE_RO)) != _PAGE_RO; }

static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }

static inline int pte_dirty(pte_t pte)		{ return pte_val(pte) & _PAGE_DIRTY; }

static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }

static inline int pte_young(pte_t pte)		{ return pte_val(pte) & _PAGE_ACCESSED; }

static inline int pte_file(pte_t pte)		{ return pte_val(pte) & _PAGE_FILE; }

static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }

static inline int pte_special(pte_t pte)	{ return pte_val(pte) & _PAGE_SPECIAL; }

static inline int pte_none(pte_t pte)		{ return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }

static inline int pte_none(pte_t pte)		{ return (pte_val(pte) & ~_PTE_NONE_MASK) == 0; }

static inline pgprot_t pte_pgprot(pte_t pte)	{ return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }

static inline pgprot_t pte_pgprot(pte_t pte)	{ return __pgprot(pte_val(pte) & PAGE_PROT_BITS); }

arch/powerpc/include/asm/pte-40x.h

+0 −1
Original line number Original line Diff line number Diff line
@@ -38,7 +38,6 @@ 
 */

 */





#define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */

#define	_PAGE_GUARDED	0x001	/* G: page is guarded from prefetch */

#define _PAGE_FILE	0x001	/* when !present: nonlinear file mapping */

#define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */

#define _PAGE_PRESENT	0x002	/* software: PTE contains a translation */

#define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */

#define	_PAGE_NO_CACHE	0x004	/* I: caching is inhibited */

#define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */

#define	_PAGE_WRITETHRU	0x008	/* W: caching is write-through */

arch/powerpc/include/asm/pte-44x.h

+0 −5
Original line number Original line Diff line number Diff line
@@ -44,9 +44,6 @@ 
 *   - PRESENT *must* be in the bottom three bits because swap cache

 *   - PRESENT *must* be in the bottom three bits because swap cache

 *     entries use the top 29 bits for TLB2.

 *     entries use the top 29 bits for TLB2.

 *

 *

 *   - FILE *must* be in the bottom three bits because swap cache

 *     entries use the top 29 bits for TLB2.

 *

 *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,

 *   - CACHE COHERENT bit (M) has no effect on original PPC440 cores,

 *     because it doesn't support SMP. However, some later 460 variants

 *     because it doesn't support SMP. However, some later 460 variants

 *     have -some- form of SMP support and so I keep the bit there for

 *     have -some- form of SMP support and so I keep the bit there for
@@ -68,7 +65,6 @@ 
 *

 *

 * There are three protection bits available for SWAP entry:

 * There are three protection bits available for SWAP entry:

 *	_PAGE_PRESENT

 *	_PAGE_PRESENT

 *	_PAGE_FILE

 *	_PAGE_HASHPTE (if HW has)

 *	_PAGE_HASHPTE (if HW has)

 *

 *

 * So those three bits have to be inside of 0-2nd LSB of PTE.

 * So those three bits have to be inside of 0-2nd LSB of PTE.
@@ -77,7 +73,6 @@ 




#define _PAGE_PRESENT	0x00000001		/* S: PTE valid */

#define _PAGE_PRESENT	0x00000001		/* S: PTE valid */

#define _PAGE_RW	0x00000002		/* S: Write permission */

#define _PAGE_RW	0x00000002		/* S: Write permission */

#define _PAGE_FILE	0x00000004		/* S: nonlinear file mapping */

#define _PAGE_EXEC	0x00000004		/* H: Execute permission */

#define _PAGE_EXEC	0x00000004		/* H: Execute permission */

#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */

#define _PAGE_ACCESSED	0x00000008		/* S: Page referenced */

#define _PAGE_DIRTY	0x00000010		/* S: Page dirty */

#define _PAGE_DIRTY	0x00000010		/* S: Page dirty */