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Commit 77e14ae6 authored by Jani Nikula's avatar Jani Nikula
Browse files

Merge tag 'gvt-next-2017-02-24' of https://github.com/01org/gvt-linux into drm-intel-fixes 



gvt-next-2017-02-24

- Min's vGPU failsafe to guard against non-secured guest
- Some guest warning fix and host error message cleanup
- Fixed vGPU type refinement for usability issue
- environ string fix from Takashi Iwai
- one kernel oops fix from Chuanxiao
- other misc fixes

Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
parents c1ae3cfa d1a513be

drivers/gpu/drm/i915/gvt/cfg_space.c

+3 −0
Original line number Diff line number Diff line
@@ -237,6 +237,9 @@ int intel_vgpu_emulate_cfg_write(struct intel_vgpu *vgpu, unsigned int offset, 
{

	int ret;



	if (vgpu->failsafe)

		return 0;



	if (WARN_ON(bytes > 4))

		return -EINVAL;

drivers/gpu/drm/i915/gvt/display.c

+83 −42
Original line number Diff line number Diff line
@@ -83,8 +83,43 @@ static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) 
	return 0;

}



static unsigned char virtual_dp_monitor_edid[GVT_EDID_NUM][EDID_SIZE] = {

	{

/* EDID with 1024x768 as its resolution */

		/*Header*/

		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,

		/* Vendor & Product Identification */

		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,

		/* Version & Revision */

		0x01, 0x04,

		/* Basic Display Parameters & Features */

		0xa5, 0x34, 0x20, 0x78, 0x23,

		/* Color Characteristics */

		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,

		/* Established Timings: maximum resolution is 1024x768 */

		0x21, 0x08, 0x00,

		/* Standard Timings. All invalid */

		0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,

		0x00, 0x40, 0x00, 0x00, 0x00, 0x01,

		/* 18 Byte Data Blocks 1: invalid */

		0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,

		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,

		/* 18 Byte Data Blocks 2: invalid */

		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,

		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,

		/* 18 Byte Data Blocks 3: invalid */

		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,

		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,

		/* 18 Byte Data Blocks 4: invalid */

		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,

		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,

		/* Extension Block Count */

		0x00,

		/* Checksum */

		0xef,

	},

	{

/* EDID with 1920x1200 as its resolution */

static unsigned char virtual_dp_monitor_edid[] = {

		/*Header*/

		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,

		/* Vendor & Product Identification */
@@ -121,6 +156,7 @@ static unsigned char virtual_dp_monitor_edid[] = { 
		0x00,

		/* Checksum */

		0x45,

	},

};



#define DPCD_HEADER_SIZE        0xb
@@ -175,10 +211,13 @@ static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num) 
}



static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,

		int type)

				    int type, unsigned int resolution)

{

	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);



	if (WARN_ON(resolution >= GVT_EDID_NUM))

		return -EINVAL;



	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);

	if (!port->edid)

		return -ENOMEM;
@@ -189,7 +228,7 @@ static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num, 
		return -ENOMEM;

	}



	memcpy(port->edid->edid_block, virtual_dp_monitor_edid,

	memcpy(port->edid->edid_block, virtual_dp_monitor_edid[resolution],

			EDID_SIZE);

	port->edid->data_valid = true;
@@ -322,16 +361,18 @@ void intel_vgpu_clean_display(struct intel_vgpu *vgpu) 
 * Zero on success, negative error code if failed.

 *

 */

int intel_vgpu_init_display(struct intel_vgpu *vgpu)

int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)

{

	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;



	intel_vgpu_init_i2c_edid(vgpu);



	if (IS_SKYLAKE(dev_priv))

		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D);

		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,

						resolution);

	else

		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B);

		return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,

						resolution);

}



/**

drivers/gpu/drm/i915/gvt/display.h

+19 −1
Original line number Diff line number Diff line
@@ -154,10 +154,28 @@ struct intel_vgpu_port { 
	int type;

};



enum intel_vgpu_edid {

	GVT_EDID_1024_768,

	GVT_EDID_1920_1200,

	GVT_EDID_NUM,

};



static inline char *vgpu_edid_str(enum intel_vgpu_edid id)

{

	switch (id) {

	case GVT_EDID_1024_768:

		return "1024x768";

	case GVT_EDID_1920_1200:

		return "1920x1200";

	default:

		return "";

	}

}



void intel_gvt_emulate_vblank(struct intel_gvt *gvt);

void intel_gvt_check_vblank_emulation(struct intel_gvt *gvt);



int intel_vgpu_init_display(struct intel_vgpu *vgpu);

int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);

void intel_vgpu_reset_display(struct intel_vgpu *vgpu);

void intel_vgpu_clean_display(struct intel_vgpu *vgpu);

drivers/gpu/drm/i915/gvt/firmware.c

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ static int expose_firmware_sysfs(struct intel_gvt *gvt) 
	int ret;



	size = sizeof(*h) + info->mmio_size + info->cfg_space_size - 1;

	firmware = vmalloc(size);

	firmware = vzalloc(size);

	if (!firmware)

		return -ENOMEM;

drivers/gpu/drm/i915/gvt/gtt.c

+26 −14
Original line number Diff line number Diff line
@@ -1825,11 +1825,8 @@ static int emulate_gtt_mmio_write(struct intel_vgpu *vgpu, unsigned int off, 
	gma = g_gtt_index << GTT_PAGE_SHIFT;



	/* the VM may configure the whole GM space when ballooning is used */

	if (WARN_ONCE(!vgpu_gmadr_is_valid(vgpu, gma),

				"vgpu%d: found oob ggtt write, offset %x\n",

				vgpu->id, off)) {

	if (!vgpu_gmadr_is_valid(vgpu, gma))

		return 0;

	}



	ggtt_get_guest_entry(ggtt_mm, &e, g_gtt_index);
@@ -2015,6 +2012,22 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) 
	return create_scratch_page_tree(vgpu);

}



static void intel_vgpu_free_mm(struct intel_vgpu *vgpu, int type)

{

	struct list_head *pos, *n;

	struct intel_vgpu_mm *mm;



	list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) {

		mm = container_of(pos, struct intel_vgpu_mm, list);

		if (mm->type == type) {

			vgpu->gvt->gtt.mm_free_page_table(mm);

			list_del(&mm->list);

			list_del(&mm->lru_list);

			kfree(mm);

		}

	}

}



/**

 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization

 * @vgpu: a vGPU
@@ -2027,19 +2040,11 @@ int intel_vgpu_init_gtt(struct intel_vgpu *vgpu) 
 */

void intel_vgpu_clean_gtt(struct intel_vgpu *vgpu)

{

	struct list_head *pos, *n;

	struct intel_vgpu_mm *mm;



	ppgtt_free_all_shadow_page(vgpu);

	release_scratch_page_tree(vgpu);



	list_for_each_safe(pos, n, &vgpu->gtt.mm_list_head) {

		mm = container_of(pos, struct intel_vgpu_mm, list);

		vgpu->gvt->gtt.mm_free_page_table(mm);

		list_del(&mm->list);

		list_del(&mm->lru_list);

		kfree(mm);

	}

	intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT);

	intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_GGTT);

}



static void clean_spt_oos(struct intel_gvt *gvt)
@@ -2322,6 +2327,13 @@ void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu, bool dmlr) 
	int i;



	ppgtt_free_all_shadow_page(vgpu);



	/* Shadow pages are only created when there is no page

	 * table tracking data, so remove page tracking data after

	 * removing the shadow pages.

	 */

	intel_vgpu_free_mm(vgpu, INTEL_GVT_MM_PPGTT);



	if (!dmlr)

		return;