[POWERPC] 85xx: Port STX GP3 board over from arch/ppc

/*

 * STX GP3 - 8560 ADS Device Tree Source

 *

 * Copyright 2008 Freescale Semiconductor Inc.

 *

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * Free Software Foundation;  either version 2 of the  License, or (at your

 * option) any later version.

 */

/dts-v1/;

/ {

	model = "stx,gp3";

	compatible = "stx,gp3-8560", "stx,gp3";

	#address-cells = <1>;

	#size-cells = <1>;

	aliases {

		ethernet0 = &enet0;

		ethernet1 = &enet1;

		serial0 = &serial0;

		pci0 = &pci0;

	};

	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		PowerPC,8560@0 {

			device_type = "cpu";

			reg = <0>;

			d-cache-line-size = <32>;

			i-cache-line-size = <32>;

			d-cache-size = <32768>;

			i-cache-size = <32768>;

			timebase-frequency = <0>;

			bus-frequency = <0>;

			clock-frequency = <0>;

		};

	};

	memory {

		device_type = "memory";

		reg = <0x00000000 0x10000000>;

	};

	soc8560@fdf00000 {

		#address-cells = <1>;

		#size-cells = <1>;

		device_type = "soc";

		ranges = <0 0xfdf00000 0x100000>;

		reg = <0xfdf00000 0x1000>;

		bus-frequency = <0>;

		compatible = "fsl,mpc8560-immr", "simple-bus";

		memory-controller@2000 {

			compatible = "fsl,8540-memory-controller";

			reg = <0x2000 0x1000>;

			interrupt-parent = <&mpic>;

			interrupts = <18 2>;

		};

		l2-cache-controller@20000 {

			compatible = "fsl,8540-l2-cache-controller";

			reg = <0x20000 0x1000>;

			cache-line-size = <32>;

			cache-size = <0x40000>;	// L2, 256K

			interrupt-parent = <&mpic>;

			interrupts = <16 2>;

		};

		i2c@3000 {

			#address-cells = <1>;

			#size-cells = <0>;

			cell-index = <0>;

			compatible = "fsl-i2c";

			reg = <0x3000 0x100>;

			interrupts = <43 2>;

			interrupt-parent = <&mpic>;

			dfsrr;

		};

		mdio@24520 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,gianfar-mdio";

			reg = <0x24520 0x20>;

			phy2: ethernet-phy@2 {

				interrupt-parent = <&mpic>;

				interrupts = <5 4>;

				reg = <2>;

				device_type = "ethernet-phy";

			};

			phy4: ethernet-phy@4 {

				interrupt-parent = <&mpic>;

				interrupts = <5 4>;

				reg = <4>;

				device_type = "ethernet-phy";

			};

		};

		enet0: ethernet@24000 {

			cell-index = <0>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x24000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <29 2 30 2 34 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy2>;

		};

		enet1: ethernet@25000 {

			cell-index = <1>;

			device_type = "network";

			model = "TSEC";

			compatible = "gianfar";

			reg = <0x25000 0x1000>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <35 2 36 2 40 2>;

			interrupt-parent = <&mpic>;

			phy-handle = <&phy4>;

		};

		mpic: pic@40000 {

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			reg = <0x40000 0x40000>;

			device_type = "open-pic";

		};

		cpm@919c0 {

			#address-cells = <1>;

			#size-cells = <1>;

			compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";

			reg = <0x919c0 0x30>;

			ranges;

			muram@80000 {

				#address-cells = <1>;

				#size-cells = <1>;

				ranges = <0 0x80000 0x10000>;

				data@0 {

					compatible = "fsl,cpm-muram-data";

					reg = <0 0x4000 0x9000 0x2000>;

				};

			};

			brg@919f0 {

				compatible = "fsl,mpc8560-brg",

				             "fsl,cpm2-brg",

				             "fsl,cpm-brg";

				reg = <0x919f0 0x10 0x915f0 0x10>;

				clock-frequency = <0>;

			};

			cpmpic: pic@90c00 {

				interrupt-controller;

				#address-cells = <0>;

				#interrupt-cells = <2>;

				interrupts = <46 2>;

				interrupt-parent = <&mpic>;

				reg = <0x90c00 0x80>;

				compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";

			};

			serial0: serial@91a20 {

				device_type = "serial";

				compatible = "fsl,mpc8560-scc-uart",

				             "fsl,cpm2-scc-uart";

				reg = <0x91a20 0x20 0x88100 0x100>;

				fsl,cpm-brg = <2>;

				fsl,cpm-command = <0x4a00000>;

				interrupts = <41 8>;

				interrupt-parent = <&cpmpic>;

			};

		};

	};

	pci0: pci@fdf08000 {

		cell-index = <0>;

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

			/* IDSEL 0x0c */

			0x6000 0 0 1 &mpic 1 1

			0x6000 0 0 2 &mpic 2 1

			0x6000 0 0 3 &mpic 3 1

			0x6000 0 0 4 &mpic 4 1

			/* IDSEL 0x0d */

			0x6800 0 0 1 &mpic 4 1

			0x6800 0 0 2 &mpic 1 1

			0x6800 0 0 3 &mpic 2 1

			0x6800 0 0 4 &mpic 3 1

			/* IDSEL 0x0e */

			0x7000 0 0 1 &mpic 3 1

			0x7000 0 0 2 &mpic 4 1

			0x7000 0 0 3 &mpic 1 1

			0x7000 0 0 4 &mpic 2 1

			/* IDSEL 0x0f */

			0x7800 0 0 1 &mpic 2 1

			0x7800 0 0 2 &mpic 3 1

			0x7800 0 0 3 &mpic 4 1

			0x7800 0 0 4 &mpic 1 1>;

		interrupt-parent = <&mpic>;

		interrupts = <24 2>;

		bus-range = <0 0>;

		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000

			  0x01000000 0 0x00000000 0xe2000000 0 0x00100000>;

		clock-frequency = <66666666>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0xfdf08000 0x1000>;

		compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";

		device_type = "pci";

	};

};