Loading Documentation/devicetree/bindings/mmc/mmc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ Optional properties: - no-sdio: controller is limited to send sdio cmd during initialization - no-sd: controller is limited to send sd cmd during initialization - no-mmc: controller is limited to send mmc cmd during initialization - extcon: phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details). - fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. The value <n> is the driver type as specified in the eMMC specification (table 206 in spec version 5.1). Loading Documentation/devicetree/bindings/mmc/sdhci-msm.txt +165 −43 Original line number Diff line number Diff line * Qualcomm SDHCI controller (sdhci-msm) Qualcomm Technologies, Inc. Standard Secure Digital Host Controller (SDHC) This file documents differences between the core properties in mmc.txt and the properties used by the sdhci-msm driver. Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards. Required properties: - compatible: Should contain: Loading @@ -10,54 +9,177 @@ Required properties: For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. New compatible string is added to support this change - "qcom,sdhci-msm-v5". - reg: Base address and length of the register in the following order: - Host controller register map (required) - SD Core register map (required) - interrupts: Should contain an interrupt-specifiers for the interrupts: - Host controller interrupt (required) - pinctrl-names: Should contain only one value - "default". - pinctrl-0: Should specify pin control groups used for this controller. - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) "core" - SDC MMC clock (MCLK) (required) "bus" - SDCC bus voter clock (optional) "xo" - TCXO clock (optional) "cal" - reference clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional) - reg : should contain SDHC, SD Core register map. - reg-names : indicates various resources passed to driver (via reg proptery) by name. Required "reg-names" are "hc_mem" and "core_mem" optional ones are "tlmm_mem" - interrupts : should contain SDHC interrupts. - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name. Required "interrupt-names" are "hc_irq" and "pwr_irq". - <supply-name>-supply: phandle to the regulator device tree node Required "supply-name" are "vdd" and "vdd-io". Required alias: - The slot number is specified via an alias with the following format 'sdhc{n}' where n is the slot number. Optional Properties: - interrupt-names - "status_irq". This status_irq will be used for card detection. - qcom,bus-width - defines the bus I/O width that controller supports. Units - number of bits. The valid bus-width values are 1, 4 and 8. - qcom,nonremovable - specifies whether the card in slot is hot pluggable or hard wired. - qcom,nonhotplug - specifies the card in slot is not hot pluggable. if card lost or removed manually at runtime, don't retry to redetect it until next reboot probe. - qcom,bus-speed-mode - specifies supported bus speed modes by host. The supported bus speed modes are : "HS200_1p8v" - indicates that host can support HS200 at 1.8v. "HS200_1p2v" - indicates that host can support HS200 at 1.2v. "DDR_1p8v" - indicates that host can support DDR mode at 1.8v. "DDR_1p2v" - indicates that host can support DDR mode at 1.2v. - qcom,bus-aggr-clk-rates: this is an array that specifies the frequency for the bus-aggr-clk which should be set corresponding to the frequency used from clk-rate. The Frequency of this clock should be decided based on the power mode in which the apps clk would run with frequency in clk-rates. - qcom,devfreq,freq-table - specifies supported frequencies for clock scaling. Clock scaling logic shall toggle between these frequencies based on card load. In case the defined frequencies are over or below the supported card frequencies, they will be overridden during card init. In case this entry is not supplied, the driver will construct one based on the card supported max and min frequencies. The frequencies must be ordered from lowest to highest. - qcom,pm-qos-irq-type - the PM QoS request type to be used for IRQ voting. Can be either "affine_cores" or "affine_irq". If not specified, will default to "affine_cores". Use "affine_irq" setting in case an IRQ balancer is active, and IRQ affinity changes during runtime. - qcom,pm-qos-irq-cpu - specifies the CPU for which IRQ voting shall be done. If "affine_cores" was specified for property 'qcom,pm-qos-irq-type' then this property must be defined, and is not relevant otherwise. - qcom,pm-qos-irq-latency - a tuple defining two latency values with which PM QoS IRQ voting shall be done. The first value is the latecy to be used when load is high (performance mode) and the second is for low loads (power saving mode). - qcom,pm-qos-cpu-groups - defines cpu groups mapping. Each cell represnets a group, which is a cpu bitmask defining which cpus belong to that group. - qcom,pm-qos-<mode>-latency-us - where <mode> is either "cmdq" or "legacy". An array of latency value tuples, each tuple corresponding to a cpu group in the order defined in property 'qcom,pm-qos-cpu-groups'. The first value is the latecy to be used when load is high (performance mode) and the second is for low loads (power saving mode). These values will be used for cpu group voting for command-queueing mode or legacy respectively. - qcom,core_3_0v_support: an optional property that is used to fake 3.0V support for SDIO devices. - qcom,scaling-lower-bus-speed-mode: specifies the lower bus speed mode to be used during clock scaling. If this property is not defined, then it falls back to the default HS bus speed mode to maintain backward compatibility. - qcom,sdr104-wa: On Certain chipsets, SDR104 mode might be unstable causing CRC errors on the interface. So there is a workaround implemented to skip printing register dumps on CRC errors and also downgrade bus speed mode to SDR50/DDR50 in case of continuous CRC errors. Set this flag to enable this workaround. - qcom,restore-after-cx-collapse - specifies whether the SDCC registers contents need to be saved and restored by software when the CX Power Collapse feature is enabled. On certain chipsets, coming out of the CX Power Collapse event, the SDCC registers contents will not be retained. It is software responsibility to restore the SDCC registers before resuming to normal operation. - qcom,force-sdhc1-probe: Force probing sdhc1 even if it is not the boot device. - qcom,ddr-config: Certain chipsets and platforms require particular settings for the RCLK delay DLL configuration register for HS400 mode to work. This value can vary between platforms and msms. If a msm/platform require a different DLL setting than the default/POR setting for HS400 mode, it can be specified using this field. In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage). - qcom,<supply>-always-on - specifies whether supply should be kept "on" always. - qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm). - qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be specified in pairs (min, max), units uV. - qcom,<supply>-current_level - specifies load levels for supply in lpm or high power mode (hpm). Should be specified in pairs (lpm, hpm), units uA. - gpios - specifies gpios assigned for sdhc slot. - qcom,gpio-names - a list of strings that map in order to the list of gpios Tlmm pins are specified as <clk cmd data> and starting with eMMC5.0 as <clk cmd data rclk> - Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" for following optional properties: - pinctrl-names - pinctrl-0, pinctrl-1,.. pinctrl-n - qcom,large-address-bus - specifies whether the soc is capable of supporting larger than 32 bit address bus width. - qcom,wakeup-on-idle: if configured, the mmcqd thread will call set_wake_up_idle(), thereby voting for it to be called on idle CPUs. - qcom,wakeup-on-idle: if configured, the mmcqd thread will call set_wake_up_idle(), thereby voting for it to be called on idle CPUs. Example: sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; aliases { sdhc1 = &sdhc_1; }; sdhc_1: qcom,sdhc@f9824900 { compatible = "qcom,sdhci-msm"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; interrupts = <0 123 0>; bus-width = <8>; non-removable; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; vdd-supply = <&pm8941_l21>; vdd-io-supply = <&pm8941_l13>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <9000 800000>; pinctrl-names = "default"; pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <6 22000>; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; }; qcom,devfreq,freq-table = <52000000 200000000>; qcom,devfreq,freq-table = <52000000 200000000>; sdhc_2: sdhci@f98a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; interrupts = <0 125 0>; bus-width = <4>; cd-gpios = <&msmgpio 62 0x1>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_on &sdc1_data_on>; vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; pinctrl-names = "default"; pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; qcom,bus-width = <4>; qcom,nonremovable; qcom,large-address-bus; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; qcom,scaling-lower-bus-speed-mode = "DDR52"; gpios = <&msmgpio 40 0>, /* CLK */ <&msmgpio 39 0>, /* CMD */ <&msmgpio 38 0>, /* DATA0 */ <&msmgpio 37 0>, /* DATA1 */ <&msmgpio 36 0>, /* DATA2 */ <&msmgpio 35 0>; /* DATA3 */ qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; qcom,pm-qos-irq-type = "affine_cores"; qcom,pm-qos-irq-cpu = <0>; qcom,pm-qos-irq-latency = <500 100>; qcom,pm-qos-cpu-groups = <0x03 0x0c>; qcom,pm-qos-cmdq-latency-us = <50 100>, <50 100>; qcom,pm-qos-legacy-latency-us = <50 100>, <50 100>; }; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; sdhc_2: qcom,sdhc@f98a4900 { qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <120 200>; }; Documentation/mmc/mmc-dev-attrs.txt +82 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,40 @@ The following attributes are read/write. force_ro Enforce read-only access even if write protect switch is off. num_wr_reqs_to_start_packing This attribute is used to determine the trigger for activating the write packing, in case the write packing control feature is enabled. When the MMC manages to reach a point where num_wr_reqs_to_start_packing write requests could be packed, it enables the write packing feature. This allows us to start the write packing only when it is beneficial and has minimum affect on the read latency. The number of potential packed requests that will trigger the packing can be configured via sysfs by writing the required value to: /sys/block/<block_dev_name>/num_wr_reqs_to_start_packing. The default value of num_wr_reqs_to_start_packing was determined by running parallel lmdd write and lmdd read operations and calculating the max number of packed writes requests. num_wr_reqs_to_start_packing This attribute is used to determine the trigger for activating the write packing, in case the write packing control feature is enabled. When the MMC manages to reach a point where num_wr_reqs_to_start_packing write requests could be packed, it enables the write packing feature. This allows us to start the write packing only when it is beneficial and has minimum affect on the read latency. The number of potential packed requests that will trigger the packing can be configured via sysfs by writing the required value to: /sys/block/<block_dev_name>/num_wr_reqs_to_start_packing. The default value of num_wr_reqs_to_start_packing was determined by running parallel lmdd write and lmdd read operations and calculating the max number of packed writes requests. SD and MMC Device Attributes ============================ Loading Loading @@ -75,3 +109,51 @@ Note on raw_rpmb_size_mult: "raw_rpmb_size_mult" is a multiple of 128kB block. RPMB size in byte is calculated by using the following equation: RPMB partition size = 128kB x raw_rpmb_size_mult SD/MMC/SDIO Clock Gating Attribute ================================== Read and write access is provided to following attribute. This attribute appears only if CONFIG_MMC_CLKGATE is enabled. clkgate_delay Tune the clock gating delay with desired value in milliseconds. echo <desired delay> > /sys/class/mmc_host/mmcX/clkgate_delay SD/MMC/SDIO Clock Scaling Attributes ==================================== Read and write accesses are provided to following attributes. polling_interval Measured in milliseconds, this attribute defines how often we need to check the card usage and make decisions on frequency scaling. up_threshold This attribute defines what should be the average card usage between the polling interval for the mmc core to make a decision on whether it should increase the frequency. For example when it is set to '35' it means that between the checking intervals the card needs to be on average more than 35% in use to scale up the frequency. The value should be between 0 - 100 so that it can be compared against load percentage. down_threshold Similar to up_threshold, but on lowering the frequency. For example, when it is set to '2' it means that between the checking intervals the card needs to be on average less than 2% in use to scale down the clocks to minimum frequency. The value should be between 0 - 100 so that it can be compared against load percentage. enable Enable clock scaling for hosts (and cards) that support ultrahigh speed modes (SDR104, DDR50, HS200). echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/polling_interval echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/up_threshold echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/down_threshold echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/enable No newline at end of file arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi +157 −0 Original line number Diff line number Diff line Loading @@ -238,6 +238,163 @@ }; }; storage_cd: storage_cd { mux { pins = "gpio77"; function = "gpio"; }; config { pins = "gpio77"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_clk_on: sdc2_clk_on { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_off: sdc2_clk_off { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_on: sdc2_cmd_on { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_off: sdc2_cmd_off { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_on: sdc2_data_on { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_off: sdc2_data_off { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_data_ds_400KHz: sdc2_data_ds_400KHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_50MHz: sdc2_data_ds_50MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_100MHz: sdc2_data_ds_100MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_200MHz: sdc2_data_ds_200MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; ap2mdm { ap2mdm_active: ap2mdm_active { mux { Loading arch/arm64/boot/dts/qcom/kona-rumi.dtsi +19 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ /* * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #include <dt-bindings/gpio/gpio.h> #include "kona-pmic-overlay.dtsi" #include "msm-audio-lpass.dtsi" Loading Loading @@ -134,3 +134,21 @@ }; }; }; &sdhc_2 { vdd-supply = <&pm8150a_l9>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pm8150a_l6>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; status = "disabled"; }; Loading
Documentation/devicetree/bindings/mmc/mmc.txt +1 −0 Original line number Diff line number Diff line Loading @@ -55,6 +55,7 @@ Optional properties: - no-sdio: controller is limited to send sdio cmd during initialization - no-sd: controller is limited to send sd cmd during initialization - no-mmc: controller is limited to send mmc cmd during initialization - extcon: phandle to external connector (Refer Documentation/devicetree/bindings/extcon/extcon-gpio.txt for more details). - fixed-emmc-driver-type: for non-removable eMMC, enforce this driver type. The value <n> is the driver type as specified in the eMMC specification (table 206 in spec version 5.1). Loading
Documentation/devicetree/bindings/mmc/sdhci-msm.txt +165 −43 Original line number Diff line number Diff line * Qualcomm SDHCI controller (sdhci-msm) Qualcomm Technologies, Inc. Standard Secure Digital Host Controller (SDHC) This file documents differences between the core properties in mmc.txt and the properties used by the sdhci-msm driver. Secure Digital Host Controller provides standard host interface to SD/MMC/SDIO cards. Required properties: - compatible: Should contain: Loading @@ -10,54 +9,177 @@ Required properties: For SDCC version 5.0.0, MCI registers are removed from SDCC interface and some registers are moved to HC. New compatible string is added to support this change - "qcom,sdhci-msm-v5". - reg: Base address and length of the register in the following order: - Host controller register map (required) - SD Core register map (required) - interrupts: Should contain an interrupt-specifiers for the interrupts: - Host controller interrupt (required) - pinctrl-names: Should contain only one value - "default". - pinctrl-0: Should specify pin control groups used for this controller. - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names. - clock-names: Should contain the following: "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required) "core" - SDC MMC clock (MCLK) (required) "bus" - SDCC bus voter clock (optional) "xo" - TCXO clock (optional) "cal" - reference clock for RCLK delay calibration (optional) "sleep" - sleep clock for RCLK delay calibration (optional) - reg : should contain SDHC, SD Core register map. - reg-names : indicates various resources passed to driver (via reg proptery) by name. Required "reg-names" are "hc_mem" and "core_mem" optional ones are "tlmm_mem" - interrupts : should contain SDHC interrupts. - interrupt-names : indicates interrupts passed to driver (via interrupts property) by name. Required "interrupt-names" are "hc_irq" and "pwr_irq". - <supply-name>-supply: phandle to the regulator device tree node Required "supply-name" are "vdd" and "vdd-io". Required alias: - The slot number is specified via an alias with the following format 'sdhc{n}' where n is the slot number. Optional Properties: - interrupt-names - "status_irq". This status_irq will be used for card detection. - qcom,bus-width - defines the bus I/O width that controller supports. Units - number of bits. The valid bus-width values are 1, 4 and 8. - qcom,nonremovable - specifies whether the card in slot is hot pluggable or hard wired. - qcom,nonhotplug - specifies the card in slot is not hot pluggable. if card lost or removed manually at runtime, don't retry to redetect it until next reboot probe. - qcom,bus-speed-mode - specifies supported bus speed modes by host. The supported bus speed modes are : "HS200_1p8v" - indicates that host can support HS200 at 1.8v. "HS200_1p2v" - indicates that host can support HS200 at 1.2v. "DDR_1p8v" - indicates that host can support DDR mode at 1.8v. "DDR_1p2v" - indicates that host can support DDR mode at 1.2v. - qcom,bus-aggr-clk-rates: this is an array that specifies the frequency for the bus-aggr-clk which should be set corresponding to the frequency used from clk-rate. The Frequency of this clock should be decided based on the power mode in which the apps clk would run with frequency in clk-rates. - qcom,devfreq,freq-table - specifies supported frequencies for clock scaling. Clock scaling logic shall toggle between these frequencies based on card load. In case the defined frequencies are over or below the supported card frequencies, they will be overridden during card init. In case this entry is not supplied, the driver will construct one based on the card supported max and min frequencies. The frequencies must be ordered from lowest to highest. - qcom,pm-qos-irq-type - the PM QoS request type to be used for IRQ voting. Can be either "affine_cores" or "affine_irq". If not specified, will default to "affine_cores". Use "affine_irq" setting in case an IRQ balancer is active, and IRQ affinity changes during runtime. - qcom,pm-qos-irq-cpu - specifies the CPU for which IRQ voting shall be done. If "affine_cores" was specified for property 'qcom,pm-qos-irq-type' then this property must be defined, and is not relevant otherwise. - qcom,pm-qos-irq-latency - a tuple defining two latency values with which PM QoS IRQ voting shall be done. The first value is the latecy to be used when load is high (performance mode) and the second is for low loads (power saving mode). - qcom,pm-qos-cpu-groups - defines cpu groups mapping. Each cell represnets a group, which is a cpu bitmask defining which cpus belong to that group. - qcom,pm-qos-<mode>-latency-us - where <mode> is either "cmdq" or "legacy". An array of latency value tuples, each tuple corresponding to a cpu group in the order defined in property 'qcom,pm-qos-cpu-groups'. The first value is the latecy to be used when load is high (performance mode) and the second is for low loads (power saving mode). These values will be used for cpu group voting for command-queueing mode or legacy respectively. - qcom,core_3_0v_support: an optional property that is used to fake 3.0V support for SDIO devices. - qcom,scaling-lower-bus-speed-mode: specifies the lower bus speed mode to be used during clock scaling. If this property is not defined, then it falls back to the default HS bus speed mode to maintain backward compatibility. - qcom,sdr104-wa: On Certain chipsets, SDR104 mode might be unstable causing CRC errors on the interface. So there is a workaround implemented to skip printing register dumps on CRC errors and also downgrade bus speed mode to SDR50/DDR50 in case of continuous CRC errors. Set this flag to enable this workaround. - qcom,restore-after-cx-collapse - specifies whether the SDCC registers contents need to be saved and restored by software when the CX Power Collapse feature is enabled. On certain chipsets, coming out of the CX Power Collapse event, the SDCC registers contents will not be retained. It is software responsibility to restore the SDCC registers before resuming to normal operation. - qcom,force-sdhc1-probe: Force probing sdhc1 even if it is not the boot device. - qcom,ddr-config: Certain chipsets and platforms require particular settings for the RCLK delay DLL configuration register for HS400 mode to work. This value can vary between platforms and msms. If a msm/platform require a different DLL setting than the default/POR setting for HS400 mode, it can be specified using this field. In the following, <supply> can be vdd (flash core voltage) or vdd-io (I/O voltage). - qcom,<supply>-always-on - specifies whether supply should be kept "on" always. - qcom,<supply>-lpm_sup - specifies whether supply can be kept in low power mode (lpm). - qcom,<supply>-voltage_level - specifies voltage levels for supply. Should be specified in pairs (min, max), units uV. - qcom,<supply>-current_level - specifies load levels for supply in lpm or high power mode (hpm). Should be specified in pairs (lpm, hpm), units uA. - gpios - specifies gpios assigned for sdhc slot. - qcom,gpio-names - a list of strings that map in order to the list of gpios Tlmm pins are specified as <clk cmd data> and starting with eMMC5.0 as <clk cmd data rclk> - Refer to "Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt" for following optional properties: - pinctrl-names - pinctrl-0, pinctrl-1,.. pinctrl-n - qcom,large-address-bus - specifies whether the soc is capable of supporting larger than 32 bit address bus width. - qcom,wakeup-on-idle: if configured, the mmcqd thread will call set_wake_up_idle(), thereby voting for it to be called on idle CPUs. - qcom,wakeup-on-idle: if configured, the mmcqd thread will call set_wake_up_idle(), thereby voting for it to be called on idle CPUs. Example: sdhc_1: sdhci@f9824900 { compatible = "qcom,sdhci-msm-v4"; aliases { sdhc1 = &sdhc_1; }; sdhc_1: qcom,sdhc@f9824900 { compatible = "qcom,sdhci-msm"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; interrupts = <0 123 0>; bus-width = <8>; non-removable; reg-names = "hc_mem", "core_mem"; interrupts = <0 123 0>, <0 138 0>; interrupt-names = "hc_irq", "pwr_irq"; vmmc-supply = <&pm8941_l20>; vqmmc-supply = <&pm8941_s3>; vdd-supply = <&pm8941_l21>; vdd-io-supply = <&pm8941_l13>; qcom,vdd-voltage-level = <2950000 2950000>; qcom,vdd-current-level = <9000 800000>; pinctrl-names = "default"; pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>; qcom,vdd-io-always-on; qcom,vdd-io-lpm-sup; qcom,vdd-io-voltage-level = <1800000 2950000>; qcom,vdd-io-current-level = <6 22000>; clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; }; qcom,devfreq,freq-table = <52000000 200000000>; qcom,devfreq,freq-table = <52000000 200000000>; sdhc_2: sdhci@f98a4900 { compatible = "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; interrupts = <0 125 0>; bus-width = <4>; cd-gpios = <&msmgpio 62 0x1>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on>; pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_on &sdc1_data_on>; vmmc-supply = <&pm8941_l21>; vqmmc-supply = <&pm8941_l13>; pinctrl-names = "default"; pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>; qcom,bus-width = <4>; qcom,nonremovable; qcom,large-address-bus; qcom,bus-speed-mode = "HS200_1p8v", "DDR_1p8v"; qcom,scaling-lower-bus-speed-mode = "DDR52"; gpios = <&msmgpio 40 0>, /* CLK */ <&msmgpio 39 0>, /* CMD */ <&msmgpio 38 0>, /* DATA0 */ <&msmgpio 37 0>, /* DATA1 */ <&msmgpio 36 0>, /* DATA2 */ <&msmgpio 35 0>; /* DATA3 */ qcom,gpio-names = "CLK", "CMD", "DAT0", "DAT1", "DAT2", "DAT3"; qcom,pm-qos-irq-type = "affine_cores"; qcom,pm-qos-irq-cpu = <0>; qcom,pm-qos-irq-latency = <500 100>; qcom,pm-qos-cpu-groups = <0x03 0x0c>; qcom,pm-qos-cmdq-latency-us = <50 100>, <50 100>; qcom,pm-qos-legacy-latency-us = <50 100>, <50 100>; }; clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; clock-names = "core", "iface"; sdhc_2: qcom,sdhc@f98a4900 { qcom,pm-qos-irq-type = "affine_irq"; qcom,pm-qos-irq-latency = <120 200>; };
Documentation/mmc/mmc-dev-attrs.txt +82 −0 Original line number Diff line number Diff line Loading @@ -8,6 +8,40 @@ The following attributes are read/write. force_ro Enforce read-only access even if write protect switch is off. num_wr_reqs_to_start_packing This attribute is used to determine the trigger for activating the write packing, in case the write packing control feature is enabled. When the MMC manages to reach a point where num_wr_reqs_to_start_packing write requests could be packed, it enables the write packing feature. This allows us to start the write packing only when it is beneficial and has minimum affect on the read latency. The number of potential packed requests that will trigger the packing can be configured via sysfs by writing the required value to: /sys/block/<block_dev_name>/num_wr_reqs_to_start_packing. The default value of num_wr_reqs_to_start_packing was determined by running parallel lmdd write and lmdd read operations and calculating the max number of packed writes requests. num_wr_reqs_to_start_packing This attribute is used to determine the trigger for activating the write packing, in case the write packing control feature is enabled. When the MMC manages to reach a point where num_wr_reqs_to_start_packing write requests could be packed, it enables the write packing feature. This allows us to start the write packing only when it is beneficial and has minimum affect on the read latency. The number of potential packed requests that will trigger the packing can be configured via sysfs by writing the required value to: /sys/block/<block_dev_name>/num_wr_reqs_to_start_packing. The default value of num_wr_reqs_to_start_packing was determined by running parallel lmdd write and lmdd read operations and calculating the max number of packed writes requests. SD and MMC Device Attributes ============================ Loading Loading @@ -75,3 +109,51 @@ Note on raw_rpmb_size_mult: "raw_rpmb_size_mult" is a multiple of 128kB block. RPMB size in byte is calculated by using the following equation: RPMB partition size = 128kB x raw_rpmb_size_mult SD/MMC/SDIO Clock Gating Attribute ================================== Read and write access is provided to following attribute. This attribute appears only if CONFIG_MMC_CLKGATE is enabled. clkgate_delay Tune the clock gating delay with desired value in milliseconds. echo <desired delay> > /sys/class/mmc_host/mmcX/clkgate_delay SD/MMC/SDIO Clock Scaling Attributes ==================================== Read and write accesses are provided to following attributes. polling_interval Measured in milliseconds, this attribute defines how often we need to check the card usage and make decisions on frequency scaling. up_threshold This attribute defines what should be the average card usage between the polling interval for the mmc core to make a decision on whether it should increase the frequency. For example when it is set to '35' it means that between the checking intervals the card needs to be on average more than 35% in use to scale up the frequency. The value should be between 0 - 100 so that it can be compared against load percentage. down_threshold Similar to up_threshold, but on lowering the frequency. For example, when it is set to '2' it means that between the checking intervals the card needs to be on average less than 2% in use to scale down the clocks to minimum frequency. The value should be between 0 - 100 so that it can be compared against load percentage. enable Enable clock scaling for hosts (and cards) that support ultrahigh speed modes (SDR104, DDR50, HS200). echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/polling_interval echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/up_threshold echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/down_threshold echo <desired value> > /sys/class/mmc_host/mmcX/clk_scaling/enable No newline at end of file
arch/arm64/boot/dts/qcom/kona-pinctrl.dtsi +157 −0 Original line number Diff line number Diff line Loading @@ -238,6 +238,163 @@ }; }; storage_cd: storage_cd { mux { pins = "gpio77"; function = "gpio"; }; config { pins = "gpio77"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_clk_on: sdc2_clk_on { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_off: sdc2_clk_off { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_clk_ds_400KHz: sdc2_clk_ds_400KHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_50MHz: sdc2_clk_ds_50MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_100MHz: sdc2_clk_ds_100MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_clk_ds_200MHz: sdc2_clk_ds_200MHz { config { pins = "sdc2_clk"; bias-disable; /* NO pull */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_on: sdc2_cmd_on { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_off: sdc2_cmd_off { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_cmd_ds_400KHz: sdc2_cmd_ds_400KHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_50MHz: sdc2_cmd_ds_50MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_100MHz: sdc2_cmd_ds_100MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_cmd_ds_200MHz: sdc2_cmd_ds_200MHz { config { pins = "sdc2_cmd"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_on: sdc2_data_on { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_off: sdc2_data_off { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <2>; /* 2 MA */ }; }; sdc2_data_ds_400KHz: sdc2_data_ds_400KHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_50MHz: sdc2_data_ds_50MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_100MHz: sdc2_data_ds_100MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; sdc2_data_ds_200MHz: sdc2_data_ds_200MHz { config { pins = "sdc2_data"; bias-pull-up; /* pull up */ drive-strength = <16>; /* 16 MA */ }; }; ap2mdm { ap2mdm_active: ap2mdm_active { mux { Loading
arch/arm64/boot/dts/qcom/kona-rumi.dtsi +19 −1 Original line number Diff line number Diff line Loading @@ -2,7 +2,7 @@ /* * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved. */ #include <dt-bindings/gpio/gpio.h> #include "kona-pmic-overlay.dtsi" #include "msm-audio-lpass.dtsi" Loading Loading @@ -134,3 +134,21 @@ }; }; }; &sdhc_2 { vdd-supply = <&pm8150a_l9>; qcom,vdd-voltage-level = <2950000 2960000>; qcom,vdd-current-level = <200 800000>; vdd-io-supply = <&pm8150a_l6>; qcom,vdd-io-voltage-level = <1808000 2960000>; qcom,vdd-io-current-level = <200 22000>; pinctrl-names = "active", "sleep"; pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on &storage_cd>; pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off &storage_cd>; cd-gpios = <&tlmm 77 GPIO_ACTIVE_LOW>; status = "disabled"; };
